Commissariat a L'energie Atomique

Soitec

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Jean-Pierre Joly

Claude Jaussaud

Michel Bruel

Jean Therme

Jean-Fr&eacute;deric Clerc

Chantal Arena

Bernard Aspar

Laurent Clavelier

Marc Zussy

Jean-Charles Souriau

Guy Parat

Gerard Nicolas

Nicolas Sillon

Olivier Faynot

Herve Achard

Michel Papapietro

Patrice Noel

Laurent Ulmer

B&eacute;atrice Biasse

A novel method makes it possible to form cavities intended to contain a liquid with determined optical properties within a film for optical use. The walls () of the cavities () are formed by plasma etching of a layer of transparent or light absorbent material () transferred onto a microtechnological substrate, the walls () having a structured profile in order to limit the parasitic phenomena of light diffusion and diffraction.

Production of cavities that can be filled with a fluid material in an optical microtechnological component

A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

Integrated circuit on high performance chip

The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Three-dimensional integrated C-MOS circuit and method for producing same

The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer () separated from a support substrate () by an intermediate zone (), the intermediate zone () being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Thin layer semi-conductor structure comprising a heat distribution layer

A process for producing a MOS-type transistor includes providing a substrate comprising a thin layer of silicon (), integral with an insulating support (), and covered with a superficial layer () of a semi-conductor material, local etching of the superficial layer to expose the silicon layer in at least one channel region, formation of an insulated gate () above the silicon layer in the channel region, and formation of a source and a drain on either side of the channel region, the source and drain extending in the layer of silicon and in the superficial layer.

Method for making a transistor on a SiGe/SOI substrate

Membrane pressure sensor containing silicon carbide and method of manufacture

Membrane pressure sensor comprising silicon carbide and method for making same

Process for the manufacture of passive and active components on the same insulating substrate

Process for transfer of a microstructure (12) from an initial substrate (10) to a final substrate (32). The process includes the following steps in sequence:

Process for selective transfer of a microstructure formed on an initial

A process for producing an improved non-volatile storage cell of the metal-ferroelectric-semiconductor type is provided. The non-volatile storage cell has at least one metal-ferroelectric-semiconductor transistor formed in a semiconductor substrate and having a source (5), a drain (6), and a gate (4). The gate is insulated from the source and the drain by a ferroelectric layer (2). The transistor has at least one lateral programming electrode (BL) in contact with the ferroelectric layer and insulated from the gate. In a preferred embodiment the cell also has a dielectric layer (7) interposed between the ferroelectric layer and the substrate. Particular utility for the present invention is found in the area of static memory devices, although other utilities are contemplated.

Non-volatile storage cell of the metal - ferroelectric - semiconductor

The invention relates to a gaseous phase chemical treatment reactor for wafers. The aim of the invention is to produce a reactor in which only the face of the wafer to be treated is in fact treated. This aim is achieved with the aid of a reactor comprising at least one treatment chamber (19) located within a main chamber (9) and connected by one of its ends to means (17) for injecting a treatment gas onto a wafer (1) and by its other end to a means (15) for securing said wafer, in that the latter is gripped between a heating susceptor or base (13) and the retaining means (15) in such a way as to seal said treatment chamber (19) and maintain within the latter a pressure below that of the main chamber (9). The invention more particularly relates to reactors for depositing tungsten on silicon wafers.

Gaseous phase chemical treatment reactor

Growing community of inventors

Saint Egreve, France

Jean-Pierre Joly