Texas Instruments Corporation

Jean-Pierre Giacalone

Anne Lombardot

Francois Theodorou

Gilbert Laurenti

Marc Couvrat

Herve Catan

Alain Boyadjian

Emmanuel Ego

Douglas E Deao

Mark L Buser

Zhenguo Gu

Shigeshi Abiko

Eric L Badi

Armelle Laine

Karim Djafarian

Vincent Gillet

Yves Masse

Gael Clave

Jean-Marc Philippe Bachot

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Laurent Ichard

Alexandra Raphaele Bireau

Frederic Nidegger

Herve Daniel

David Russell

N M Ganesh

An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (), and an interface () coupling said random access memory () to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.

Hardware extension for accelerating fractional integer division within 3D graphics and MP3 applications

An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.

Unified interleaver/de-interleaver

An arithmetic unit, for example a multiply and accumulate (MAC) unitfor a processing engine includes a partial product reduction treeThe partial product reduction tree will generate carry results and provides a final output to a final adderconnected to the partial production reduction tree. Unbiased rounding logicis provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signalwhich is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero. Through the use of a carry propagation tree to predict, or anticipate zeros on the N least significant bits, unbiased rounding can be effected without a time penalty in that a carry propagation tree can be configured to be at least a rapid as the carry propagation of the final adder. Where a zero anticipation function is provided, this can also be mapped onto the carry propagation tree, thus providing an efficient hardware implementation through sharing of that hardware between functions.

Rounding mechanisms in processors

A processing device () includes three hardware extensions: a motion estimation extension, a pixel interpolation extensionand a DCT/iDCT extension. The hardware extensions perform functions which would otherwise be highly processor intensive, resulting in high power consumption and/or low quality video/imaging processing. The processing devicecould be used, for example, in a mobile videophone

Hardware extensions for image and video processing

An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.

Bit field processor

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said first and second operands, a Wallace tree adder for reducing the partial products and for selectively arithmetically combining the reduced partial products with said third operand, a final adder for generating a final sum, and a saturation circuitry for selectively rounding or saturating said final sum is provided. A dual MAC unit is also provided.

Multiplier accumulator circuits

A zero anticipation mechanism for an arithmetic unit of a processing engine includes an array of cells interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result prior to the arithmetic unit completing an arithmetic operation.

Zero anticipation method and apparatus

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Jean-Pierre Giacalone