Texas Instruments Corporation

Jean-Pierre Dolait

Gene A Frantz

Masashi Hashimoto

John Victor Moravec

A memory circuit () having features specifically adapted to permit the memory circuit () to serve as a video frame memory is disclosed. The memory circuit () contains a dynamic random access memory array () with buffers () on input and output data ports () thereof to permit asynchronous read, write and refresh accesses to the memory array (). The memory circuit () is accessed both serially and randomly. An address generator () contains an address buffer register () which stores a random access address and an address sequencer () which provides a stream of addresses to the memory array (). An initial address for the stream of addresses is the random access address stored in the address buffer register ().

SDRAM with command decoder coupled to address registers

SDRAM with command decoder, address registers, multiplexer, and sequencer

A memory circuit ( ) having features specifically adapted to permit the memory circuit ( ) to serve as a video frame memory is disclosed. The memory circuit ( ) contains a dynamic random access memory array ( ) with buffers ( ) on input and output data ports ( ) thereof to permit asynchronous read, write and refresh accesses to the memory array ( ). The memory circuit ( ) is accessed both serially and randomly. An address generator ( ) contains an address buffer register ( ) which stores a random access address and an address sequencer ( ) which provides a stream of addresses to the memory array ( ). An initial address for the stream of addresses is the random access address stored in the address buffer register ( ).

Process of operating a DRAM system

Synchronous DRAM with control data buffer

Process of using a DRAM with address control data

Synchronous data system with control data buffer

Memory device for transferring streams of data

Process for controlling reading data from a DRAM array

System with control data buffer for transferring streams of data

Synchronous DRAM system with control data

A memory circuit ( ) having features specifically adapted to permit the memory circuit ( ) to serve as a video frame memory is disclosed. The memory circuit ( ) contains a dynamic random access memory array ( ) with buffers ( ) on input and output data ports ( ) thereof to permit asynchronous read, write and refresh accesses to the memory array ( ). The memory circuit ( ) is accessed both serially and randomly. An address generator ( ) contains an address buffer register ( ) which stores a random access address and an address sequencer ( ) which provides a stream of addresses to the memory array ( ). An initial address for the stream of the addresses is the random access address stored in the address buffer register ( ).

Synchronous data transfer system

Synchronous DRAM System with control data

Synchronous DRAM device having a control data buffer

A memory circuit (,) having features specifically adapted to permit the memory circuit (,) to serve as a video frame memory is disclosed. The memory circuit (,) contains a dynamic random access memory array (,) with buffers (,) on input and output data ports (,) thereof to permit asynchronious read, write and refresh accesses to the memory array (,). The memory circuit (,) is accessed both serially and randomly. An address generator (,) contains an address buffer register (,) which stores a random access address and an address sequencer (,) which provides a stream of addresses to the memory array (,). An initial address for the stream of addresses is the random access address stored in the address buffer register (,).

Process of synchronously writing data to a dynamic random access memory array

A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and ouput data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Memory circuit accommodating both serial and random access, having a

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Villeneuve-Loubet, France

Jean-Pierre Dolait