Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (Crolles 2) Sas

Centre National De La Recherche Scientifique

Université´ D'aix-Marseille

Stmicroelectronics (Rousset) Sas

Jean-Philippe Noel

Bastien Giraud

Olivier Thomas

Sylvain Clerc

Fady Abouzeid

Yvain Thonnart

Philippe Flatresse

Henri-Pierre Charles

Maha Kooli

Matthieu Le Boulaire

Maud Vinet

Philippe Roche

Adam Makosiej

Jean-Michel Portal

Lorenzo Ciampolini

Kevin Mambu

Alexandre Levisse

Kaya Can Akyel

Bertrand Pelloux-Prayer

Emilien Bourde-Cice

Avishek Biswas

Valentin Egloff

Reda Boumchedda

Réda Boumchedda

The present description concerns a system comprising at least one first and one second memory circuits; and a direct data transfer circuit which is adapted to receiving specific instructions originating from an external processor, and to decoding specific instructions comprising: a specific instruction SET_REGION of definition of a sub-region in the first memory circuit towards and from which the data will be transferred; and a specific instruction of transfer between said sub-region and the second memory circuit, the specific transfer instruction comprising a first address field containing the relative coordinates, in said sub-region, of a first reference cell.

Direct data transfer system

A static random access memory device includes a memory matrix provided with at least one set of SRAM memory cells and a circuit for initializing cells of the set, the setting circuit being able to carry out various setting types and in particular a 'deterministic' setting in which the cells are established at an imposed value and to carry out a “free” setting in which the cells are established at a value that depends on their manufacturing method.

SRAM with reconfigurable setting

The present description concerns a memory device () including a non-volatile memory circuit (); a buffer memory circuit () comprising a volatile memory circuit (); an input-output circuit (); a first data link () coupling the non-volatile memory circuit () to the buffer memory circuit (); a second data link () coupling the buffer memory circuit () to the input-output circuit (); and a control circuit (), wherein the buffer memory circuit () is adapted to implementing calculations having as operands data stored in the volatile memory circuit ().

Buffer memory adapted to implment calculations having operands as data

A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical '1', is greater than a predetermined threshold.

Circuit for detection of predominant data in a memory cell

A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

Memory circuit capable of implementing calculation operations

A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.

Memory circuit

A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

System comprising a memory capable of implementing calculation operations

SRAM memory having a reduced leakage current

A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.

A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M&#x2212;1, are coupled together.

Partitioned memory circuit capable of implementing calculation operations

A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.

Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof

A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.

An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

Integrated circuit comprising transistors with different threshold voltages

A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference ('BGPD') of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Method for controlling an integrated circuit

An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.

Growing community of inventors

Montbonnot Saint Martin, France

Jean-Philippe Noel