Cerebras Systems Inc.

Advanced Micro Devices Corporation

Emc IP Holding Company LLC

Alcatel Lucent

Alcatel-lucent USA Inc.

Logitech Europe S.a.

Jean-Philippe Fricker

Philip Arnold Ferolito

Paul Kennedy

Frank Jun

Donald C Lewis

Bernard Kasser

Michael E James

Gilles Van Ruymbeke

Marc Ledin

Tim Botsford

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

Apparatus and method for fabricating multi-die interconnection using lithography process

Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.

Apparatus and method for securing components of an integrated circuit

Systems and methods include an integrated circuit assembly that includes a semiconductor substrate; a heat transfer element; and an ambulatory thermal interface arranged between the semiconductor substrate and the heat transfer element, the ambulatory thermal interface comprising: a thermally conductive material, and a friction reduction material, wherein: the thermally conductive material is arranged along a surface of the heat transfer element, the friction reduction material is arranged along a surface of the semiconductor substrate, opposing surfaces of the thermally conductive material and the friction reduction material define a slidable interface when placed in contact.

Apparatuses and methods for implementing a sliding thermal interface between substrates with varying coefficients of thermal expansion

Apparatus and method for multi-die interconnection

An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

Apparatus and method for securing substrates with varying coefficients of thermal expansion

The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately include any other suitable components.

Systems and methods for powering an integrated circuit having multiple interconnected die

The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductorcan include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.

System and method for alignment of an integrated circuit

A method for fabricating an orifice in a semiconductor which can include: removing a first depth of the semiconductor using a first material removal technique and removing a second depth of the semiconductor using a second material removal technique. The method can optionally include: adding a sacrificial layer of material and reducing a depth of the semiconductor by a friction-based material removal technique. In examples, the method fabricates a wafer-scale processor with a set of fastening features.

Systems and methods for precision fabrication of an orifice within an integrated circuit

A system and method for fabricating an orifice in a multi-layered semiconductor substrate and singulation of the semiconductor substrate includes adding a sacrificial layer of material to a first surface of a semiconductor substrate; subsequently, removing a first radius of a first depth of material from the semiconductor substrate along a direction normal to the first surface, the removal of the first depth of material uses a first removal technique that removes the first depth of material; and removing a second radius of a second depth of material from the semiconductor substrate along the direction normal to the first surface based on the removal of the first depth of material, the removal of the second depth of material uses a second removal technique.

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

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Mountain View, CA, United States of America

Jean-Philippe Fricker