Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (rousset) Sas

Jean-Philippe Colonna

Sami Oukassi

Jean Brun

Sylvain Joblot

Guillaume Savelli

Perceval Coudrain

Bertrand Chambion

Benoit Besancon

Didier Campos

Stéfan Landis

Rafael Augusto Prieto Herrera

Olivier Guiller

Louis-Michel Collin

Luc Frechette

Thierry Mourier

Rafael Prieto Herrera

Christophe Aumont

A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.

Process for collectively curving a set of electronic chips

A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.

Wafer-level process for curving a set of electronic chips

A method for manufacturing a cooling circuit on at least one integrated circuit chip includes producing a cooling circuit on a first face of the chip. Producing the cooling circuit includes forming a definition pattern of the cooling circuit on the first face of the chip, the pattern having at least one layer of a sacrificial material; coating the pattern with at least one resin layer; and at least partially removing the sacrificial material from the pattern so as to open the cooling circuit.

Method of manufacturing a cooling circuit on an integrated circuit chip using a sacrificial material

A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.

Heat-transferring and electrically connecting device and electronic device

An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

Electronic device provided with a thermal dissipation member

Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

Method for collective (wafer-scale) fabrication of electronic devices and electronic device

The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Method for manufacturing a conducting contact on a conducting element

A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.

Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device

The present invention relates to methods of manufacturing a structure having semi-conductor material nanocrystals on a dielectric material substrate by chemical vapour deposition (CVD), the method including at least: i) contacting a surface of a dielectric layer present on a substrate with a first gaseous precursor, by CVD, to form nanocrystal nuclei on the surface of a the dielectric layer; ii) contacting the nanocrystal nuclei with a second gaseous precursor, by CVD, to selectively deposit nanocrystal semi-conductor material only on the nuclei and to grow nanocrystals on the nuclei, each nanocrystal having an exposed surface; and iii) forming a nitride layer only on the exposed surface of each nanocrystal by contacting the nanocrystals with a mixture including at least the second gaseous precursor and a third gaseous precursor to terminate the growth of said nanocrystals and to selectively and stoichiometrically deposit the nitride layer on the exposed surface, wherein a material of said nanocrystal nuclei is compatible with a material of said dielectric layer, each of i), ii) and iii) are carried out in a same chamber, and the first gaseous precursor, the second gaseous precursor and the mixture of the second gaseous precursor with the third gaseous precursor are introduced into the chamber in a continuous flow.

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Corenc, France

Jean-Philippe Colonna