International Business Machines Corporation

Jean-Paul J Nuez

Pierre B Mollier

Gerard M Lebesnerais

Pascal R Tannhof

Francois X Delaporte

Michel J Grandguillot

Gerard Boudon

Daniel Ballatore

Robert M Hornung

Ieng Ong

Franck Wallart

Anne-Marie Lamouroux

The base circuit comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages and a push-pull output buffer stage connected between second and third supply voltages. The push-pull output buffer stage comprises a pull-up transistor and a pull-down transistor connected in series with the circuit output node coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by the preamplifier. Both branches of the preamplifier are tied at a first output node (M). The first branch comprises a logic block performing the desired logic function of the base circuit that is connected through a load rsistor to the second supply voltage. The logic block consists of three parallel-connected input NPN transistors, whose emitters are coupled together at the first output node for NOR operation. The second branch is comprised of a biasing/coupling block connected to the second supply voltage and coupled to the first output node and to the base (B) node of the pull-down transistor. This block ensures both the appropriate polarization of the nodes in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal from node M to node B in AC, when input transistors of the logic block are ON. and base nodes. An anti-saturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

Self-referenced current switch logic circuit with a push-pull output

According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a characteristic of this embodiment that the structure of CMOS interface (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH-BE) to VH range.

BICMOS logic circuit with full swing operation

A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..

True/complement generator employing feedback circuit means for

Integrated read-only memory including nxm memory cells located at the intersections of m bit lines and n word lines in which binary information of a first type is represented by the presence of a connection to a transistor in a cell, the base of said transistor being connected to a word line while its emitter is connected to a bit line, and in which binary information of a second type is represented by the absence of a connection to a transistor in a cell, said memory being of the type in which reading is ensured by means of m read transistors the emitters of which are connected to the bit lines while their bases are connected to a reference voltage supply, the improvement comprising read transistors arranged into k adjacent sets of m/k consecutive elements, k being an integer submultiple of m, the transistors of each set being provided in the same collector epitaxial bed in a semiconductor substrate with a collector contact common to all the transistors, the collector contact of each set being connected to a read circuit.

High density integrated read-only memory

An implanted resistor structure for semiconductor integrated circuit devices is formed by a double ion-implantation providing a high breakdown voltage resistor.

Breakdown voltage resistor obtained through a double ion-implantation

Arrangements are described for correcting the voltage coefficient of resistance (VCR) of resistors integral with a semiconductor body and, more particularly, for correcting the VCR of resistors implanted in a semi-conductor body. Resistors typically comprising a resistive region of a first conductivity type formed in an isolated layer of opposite conductivity type which isolated layer, in general, includes an epitaxial layer passivated by a dielectric layer. A metal layer is formed on the dielectric layer and covers, at least partially, the resistive layer. The metal layer is brought to a suitable potential to produce opposite variations in the resistance with respect to variations created by the epitaxial layer.

Arrangement for correcting the voltage coefficient of resistance of

A method and structure for correcting the voltage coefficient of resistance (VCR) of a resistor in a semiconductor body is described. The resistor may be diffused or ion implanted of one conductivity and formed in an isolated layer of the opposite type of conductivity. The layer is typically an epitaxial layer. A potential V.sub.1 is applied to one end of the resistor and a potential V.sub.2 being applied to the opposite end. The method provides means for controlling variations of the potential difference between the resistive region and the epitaxial layer, either to minimize them or to cause the distortions generated by such variations to be compensated for by equal distortions of opposite directions, such that the overall distortion will be equal to zero. There is provided means to cause the potential of the epitaxial layer to reach a suitable value, preferably a value that varies in the same manner as the average value of the resistor whose VCR is to be corrected.

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Mennecy, France

Jean-Paul J Nuez