Alcatel Cit

Jean-Paul Etienne

Jean-Louis Jeandot

A digital bit stream from a first synchronous link is timed by a first clock and is to be sent over a second synchronous link timed by a second clock. A device for justifying the bit stream at regular intervals includes a buffer memory. Respective pointers supply buffer memory write and read addresses. A value indicating how full the buffer memory is is calculated and compared to first and second threshold values to produce a justification command signal. The first and second variable threshold values are determined according to the phase difference between the header of a row received from the first link and the header of a row sent at the same time on the second link. The device finds an application in gateways at the input of and in telecommunication networks using the synchronous digital hierarchy.

Device for justifying a digital bit stream at regular intervals

A device for filtering positive dejustification jitter of a digital bit stream includes a phase-locked loop for slaving the timing of a signal representative of the read timing of a buffer memory into which the dejustified digital bit stream is written to the timing of a signal representative of the write timing of the buffer memory. The device applies low-pass filtering and determines the actual justification rate of the digital bit stream and deduces therefrom the difference justification rate, i.e. the difference between the actual rate and a nominal justification rate of the digital bit stream. It systematically eliminates phase shifts due to positive dejustification from the signal representative of the buffer memory write timing, regenerates phase shifts of the signal in numbers corresponding to the nominal justification rate, and regenerates phase shifts of the signal in numbers corresponding to the difference justification rate and smooths the phase shifts.

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St Quay-Perros, France

Jean-Paul Etienne