Mentor Graphics (holdings) Ltd.

Siemens Industry Software Gmbh

Jean-Paul Clavequin

Philippe Diehl

Pascal Couteaux

Charles W Selvidge

Jean-Marc Brault

Laurent Vuillemin

Each reconfigurable hardware modeling circuit of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a model computation subsystem configurable either to model elements of a circuit design, or to serve as a testbench element, or both, and a network subsystem comprising: network circuitry and signal reduction circuitry, the signal reduction circuitry configurable to perform a signal reduction function, the signal reduction function combining a plurality of status signals into a single status signal, the plurality of status signals comprising status signals received from one or more reconfigurable hardware modeling circuits in the plurality of reconfigurable hardware modeling circuits. Alternatively or additionally, each network circuit of a plurality of network circuits in the reconfigurable hardware modeling device may comprise signal reduction circuitry configurable to perform the signal reduction function.

Reduce/broadcast computation-enabled switching elements in an emulation network

In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Latency adjustment between integrated circuit chips

Synchronized communication between integrated circuit chips

Growing community of inventors

Sevres, France

Jean-Paul Clavequin