Université´ D'aix-Marseille

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics (Rousset) Sas

Stmicroelectronics (Crolles 2) Sas

Stmicroelectro (Crolles 2) Sas

Centre National De La Recherche Scientifique-Cnrs

Jean-Michel Portal

Vincenzo Della Marca

Philippe Boivin

Elisa Vianello

Julien Gasquez

Jean-Pierre Walder

Laurent Grenouillet

Olivier Thomas

Bastien Giraud

Romain Wacquez

Jean-Philippe Noel

Adam Makosiej

Marios Barlas

François Andrieu

Jean Coignus

Tifenn Hirtzlin

Santhosh Onkaraiah

Djohan Bonnet

Eduardo Esmanhotto

Thomas-Medhi Benoist

Valentin Egloff

Yves Maneglia

Haithem Ayari

Marc Bocquet

Alexis Krakovinsky

A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M≥1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

Memory cell, electronic circuit comprising such cells, related programming method and multiplication and accumulation method

A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.

Self-referenced and regulated sensing solution for phase change memory with ovonic threshold switch

The present description concerns a memory device () including a non-volatile memory circuit (); a buffer memory circuit () comprising a volatile memory circuit (); an input-output circuit (); a first data link () coupling the non-volatile memory circuit () to the buffer memory circuit (); a second data link () coupling the buffer memory circuit () to the input-output circuit (); and a control circuit (), wherein the buffer memory circuit () is adapted to implementing calculations having as operands data stored in the volatile memory circuit ().

Buffer memory adapted to implment calculations having operands as data

Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.

The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.

Non-volatile memory allowing a high integration density

A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.

Method for forming a non-volatile memory cell, non-volatile memory cell formed according to said method and microelectronic device comprising such memory cells

A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.

Programmable-resistance non-volatile memory

Growing community of inventors

Saint-Savournin, France

Jean-Michel Portal