North American Philips Corporation

North American Philips Corp., Signetics Div.

Jean-Michel J Labrousse

Gerrit A Slavenburg

Gerrit Ary Slavenburg

A processing device includes an imitation multiport memory circuit (10) interconnecting inputs and outputs of a group of functional units (F1, . . . FN), all operating under control of a single series of very long program instructions. The memory circuit (10) comprises a plurality of separate memory units (15), each having a read port (12) connected to a respective functional unit input, and a crossbar switching circuit (18) connected between the functional unit outputs and write ports of the separate memory units. The memory circuit (10) provides substantially the same performance as a true multiport memory but requires a smaller circuit area, allowing a larger processing device to be integrated in one chip than previously. Collisions for access to a memory unit write port can be resolved without rescheduling by use of a delay element (21,70) and/or an additional write port (82) to a memory unit.

VLIW processing device including improved memory for avoiding collisions

A highly parallel and pipelined computer processor such as a pipelined very long instruction word (VLIW) processor having a plurality of arithmetic and logic units (ALUs) which process computer operations in parallel to speed up the operation of the computer. Operations issued during the branch delay period following conditional jump operations are conditioned on the outcomes of the condition evaluation of such conditional jump operations that have not yet percolated through the instruction issue pipeline, by matching a field in the operation to path information generated by a branch control unit. Operations that succeed are allowed to proceed and the effects of unsuccessful operations are disabled. This allows a form of look-ahead computation after a conditional branch which is particularly attractive for a VLIW processor having a large number of parallel functional units and allows useful work to be done in the branch delay periods. Optionally, only such operations that affect the programmer-visible state of the computer are so conditioned, e.g., store operations to memory, program flow control operations and operations that raise exception conditions. The matching algorithm can be implemented such that an operation is enabled on a single path or on an arbitrary set of paths.

VLIW processor which uses path information generated by a branch control

A program-controlled processing device includes a multiport memory circuit providing a plurality of storage locations. First and second data ports of the memory circuit provide parallel access to different locations in accordance with first and second addresses encoded in the program instructions. Bypass means is provided for coupling the second data port to the first data port to simulate parallel access to the same location when desired. The bypass means is controlled directly by the program instructions, by means of a separate bypass control field or by a special value of one of the two addresses. There is thus no need for a run-time comparison of addresses before each memory access, leading to a faster operation of the memory circuit.

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Palo Alto, CA, United States of America

Jean-Michel J Labrousse