Freescale Semiconductor,inc.

Agile Power Switch 3d-integration Apsi3d

Other

Irt Saint Exupery (aese)

Ecole Nationale D'ingenieurs De Tarbes

Irt Antoine De Saint Exupery

Institut Catholique D'arts Et Metiers (icam)

Jean-Michel Francis Reynes

Evgueniy Nikolov Stefanov

Ivana Deram

Alain Deram

Jacques Pierre Henri Favre

Stephane Alves

Blandino Lopes

Raphaël Riva

Joel Margheritta

Philippe Lance

Yann Weber

Baptiste Louis Jean Trajin

Frederico Morancho

Adeline Feybesse

Isabelle Majoral

Renaud André Lacabanne

Jean-Pierre Pujo

Eric Marty

Paul-Etienne Joseph Vidal

Bernard José Charles Du Trieu De Terdonck

Jean-Baptiste Sauveplane

Claudia Cadile

Jean-Pierre Bernard Marie Fradin

Some embodiments are directed to a method of determining a sintering thermal impedance of a sintering layer by: providing a substrate having a predetermined substrate thermal impedance and disposing the sintering layer on the substrate forming with the sintering layer a stack. Placing at least one semiconductor die, that includes a semiconductor element with at least two element electrodes on the sintering layer. Injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element. Heating the stack with a predetermined heat power and determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter. Measuring a stack temperature and determining a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature and dividing by the predetermined heat power, and subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

Method of determining thermal impedance of a sintering layer and a measurement system

Some embodiments are directed to a semiconductor power device and a method of assembling such a device is provided. The semiconductor power device includes a first substrate, a second substrate and an interconnect structure. The first substrate includes a switching semiconductor element, a first electrically conductive layer(s) and a first receiving element. The second substrate includes a second receiving element and a second electrically conductive layer(s). The interconnect structure provides an electrical connection between the first electrically conductive layer and the second electrically conductive layer. The interconnect structure further includes a plurality of interconnect elements of an electrical conductive material. At least one of the plurality of interconnect elements is an alignment interconnect element. The alignment interconnect element is partially received by the first receiving element and is partially received by the second receiving element for aligning a relative position of the first substrate with respect to the second substrate.

Semiconductor power device and a method of assembling a semiconductor power device

Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.

Semiconductor power device comprising additional tracks and method of manufacturing the semiconductor power device

A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Semiconductor device and method of forming a semiconductor device

A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer. The first region and second region are driven into the semiconductor layer so as to form a pre-control region of the first conductivity type extending into the semiconductor layer from the surface and under a portion of the control region and a graded body region of the second conductivity type extending into the semiconductor layer under the pre-control region. A body region is formed by providing semiconductor material of the second conductivity type to the outlined first portion. The body region extends into the pre-control region. A current electrode region is formed in the body region.

A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region.

Field-effect semiconductor device and method of forming the same

The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device, and a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element. The present invention also relates to a method of forming a temperature sensing element for integration with a semiconductor device.

Temperature sensing device

A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.

Power semiconductor device

A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Method of forming a semiconductor device having an active area and a termination area

A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die.

Power semiconductor device and method of manufacturing a power semiconductor device

A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (). Each individual cell comprises a plurality of radially extending branches () having source regions () within base regions (). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region () of the extending branches merge together to form a single and substantially uniformly doped base region () surrounding drain islands () at the surface of the semiconductor substrate ().

Power semiconductor device with a base region and method of manufacturing same

The present invention relates to a method of forming a diode ( ) for integration with a semiconductor device comprising the steps of providing a layer ( ) of semiconductor material, forming a dielectric layer ( ) over the layer of semiconductor material, introducing a first conductivity type dopant into the dielectric layer ( ), forming a semi-conductive layer ( ) over the dielectric layer ( ), introducing a second conductivity type dopant into a first region ( ) of the semi-conductive layer and re-distributing the first conductivity type dopant from the dielectric layer ( ) into the semi-conductive layer ( ) so as to form a second region ( ) of the first conductivity type dopant in the semi-conductive layer ( ), the second region ( ) being adjacent the first region ( ) so as to provide a P/N junction of the diode ( ).

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Pompertuzat, France

Jean-Michel Francis Reynes