Cadence Design Systems, Inc.

Jean-Michel Fernandez

Gerard Tarroux

A simulator for a design of an electronic system includes high-level delay models for architecture resources such as ASICs, CPUs, and busses, for example. The delay models of pipelined ASICs compute static pipeline delays which are then implemented by the system simulator. The ASIC delay models are generic, dynamic, incremental and not intrusive.

Modeling an ASIC based on static pipeline delays

A method and system reduces the complexity of functions within a Boolean network by breaking the network at certain nodes. Before the flattening phase of a technology independent optimization, the present invention estimates the on-set and off-set complexities of each node of the network. The complexities are estimated by considering the type of function represented by the node, the estimated complexities of any child nodes, and the number of variables in the support of the node. If a node's estimated complexity exceeds a defined complexity limit, then the network is preferably broken at that node. A new node of the same type as the complex node is created, and child nodes of the complex node are appended to the newly created node. In addition, an intermediate node is created as a child of the complex node and the child nodes are removed from the complex node. Removing the child nodes from the complex node reduces the complexity of the node and allows the minimization phase to better optimize the network.

Growing community of inventors

Paris, France

Jean-Michel Fernandez