Atmel Corporation

Atmel Rousset S.a.s.

Jean Michel Daga

Benoit Godard

Caroline Papaix

Jeanine Guichaoua

Godard Benoit

Olivier Ginez

A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.

Error detecting/correcting scheme for memories

A method and system for providing a content addressable memory cell (CAM) as well as the CAM are disclosed. In one aspect, the method and system include providing a plurality of memory cells, at least one search line and at least one match line. Each of the CAM cells includes a FLOating gate Tunnel OXide (FLOTOX) element. The FLOTOX element includes a single floating gate transistor and a high voltage select transistor and can store at least a portion of a data word. Each CAM cell also preferably includes at least one low voltage transistor capable of comparing the portion of data word stored in the FLOTOX element with the portion of searched word. The search line(s) provide search word(s). The comparator(s) are connected with the search line(s) and the memory cells. The comparator(s) compare the data word stored by the portion of the plurality of memory cells and the search word. The match line(s) indicate whether the search word matches the data word stored by the portion of the plurality of memory cells.

Content addressable memory cell having a single floating gate transistor

A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline, a direct current amplification circuit electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, a current-to-voltage conversion circuit for converting the sensed current to a voltage and a voltage amplification circuit for amplifying the voltage at the sense amp output. The sense amplifier can be implemented using standard CMOS components and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.

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Peynier, France

Jean Michel Daga