Atmel Corporation

Micron Technology Incorporated

Jean-Michel Daga

Jimmy Fort

Philippe Bruno Bauser

Marylene Combe

Eric Carman

Marc Merandat

Stephane Ricard

Emmanuel Racape

Caroline Papaix

Techniques for sensing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop.

Techniques for sensing a semiconductor memory device

Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the technique(s) may be realized as a semiconductor memory device comprising a plurality of memory cells arranged in an array of rows and columns and data sense amplifier circuitry coupled to at least one of the plurality of memory cells. The data sense amplifier circuitry may comprise first amplifier circuitry and resistive circuitry, wherein the first amplifier circuitry and the resistive circuitry may form a feedback loop.

Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array.

Techniques for controlling a semiconductor memory device

Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.

A charge pump is configured to receive an external voltage level and generate a high voltage level, wherein the high voltage level is higher than the external voltage level. A memory control circuit is configured to receive the external voltage level and the high voltage level, and to select one of the voltage levels. A memory array, with a word line and a bit line, is configured to receive the external and high voltage levels at the word line and the high voltage levels at the bit line. A word line driver is configured to provide the external and high voltage levels to the word line. A bit line selector is configured to select the bit line and receive the high, external, and regulated voltage levels. A bit line driver is configured to provide the external voltage levels to the bit line selector.

Method and apparatus for a dual power supply to embedded non-volatile memory

An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a charge pump that is preferably a regulated charge pump. The charge pump is selectively controlled by a slew rate control circuit when FN tunneling injection is detected by a voltage level detection circuit at a predetermined threshold voltage level.

Apparatus and method for charge pump slew rate control

A sense amplifier circuit and a method for reading a memory cell. A circuit comprises a first bit line associated with a memory cell. A first input of a latch is coupled to the first bit line and a second input of the latch is coupled to a second node. There is a means for biasing the first input and the second input of the latch to a differential voltage between the first node coupled to the first bitline and the second node. There is also a means for switching the latch according to memory cell current. There is also a means for producing an output signal indicating the direction of switch. A method of reading a memory cell comprises precharging a first bit line which is associated with a memory cell. The memory cell current is driven according to the programmed state of the memory cell. Latch circuitry is biased based on a differential voltage between a first node coupled to the first bit line and a second node. The latch circuitry is then activated and the latch circuitry switches according to the memory cell current. An output signal indicating the direction of the latch circuitry's switch is then produced.

High-speed, self-synchronized current sense amplifier

A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, and a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline. To sense multiple current levels and multiple stored bits per memory cell, multiple direct current amplification circuits are electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, multiple current-to-voltage conversion circuits for converting a sensed current to a voltage, and a multiple voltage amplification or inverter circuits for amplifying the voltage and detecting a multitude of current levels. The multitude of current levels are converted or decoded into multiple bits. The sense amplifier can be implemented using standard CMOS components and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.

Sense amplifier circuit for parallel sensing of four current levels

A self-adaptive programming circuit for EEPROM is used to automatically tune an erase or write delay, providing an improved programming window. The programming circuit may also provide improvements in data retention for programmed memory cells. The invention can be applied more particularly in the field of EEPROM memories capable of page mode writing operations.

Self-adaptive program delay circuitry for programmable memories

The present invention features use of PMOS devices to realize switches of an integrated circuit charge pump, while maintaining a maximum voltage drop (lower than VDD) on each transistor. The charge pump includes a pumping capacitor connected to a pumping node, a first PMOS device connected to an input node, a second PMOS device connected to an output node, a third PMOS device electrically communicating with the first PMOS device, and an auxiliary capacitor connected to the first PMOS device. The first PMOS device is configured to connect the pumping node to the input node when the pumping capacitor is not boosted. The second PMOS device is configured to transfer electrical current from the pumping node to the output node when the pumping capacitor is not boosted.

High efficiency, low cost, charge pump circuit

An EEPROM memory circuit in which the loading of the column latches can be performed simultaneously with reading of the memory array. In this memory circuit, the data input connects directly to the column latches, leaving the bit lines open for memory reading by the sense amplifiers, which is connected directly to the bit lines. Two separate Y address decoders, one feeding into the column latches and the other into the bit line select circuit, provide column latch and bit line selection respectively.

Growing community of inventors

Rousset, France

Jean-Michel Daga