Intel Corporation

Cortina Systems Corporation

Inphi Corporation

Jean-Michel Caia

Juan-Carlos Calderon

Jing Ling

Arun Zarabi

Vivek Joshi

Anguo Tony Huang

Soowan Suh

Arash Farhoodfar

Steve John Clohset

Alejandro Lenero Beracoechea

Vasan Karighattam

Michael Raymond Miller

Aws Shallal

Mark T Feuerstraeter

Dennis Albert Doidge

Miriam Qunell

Eduard Lecha

Edward J Pullin

Theron Paul Niederer

Rodrigo Gonzalez

Jeff Fedders

Jasson Flinn

Augusto Alcantara

Scott Feller

Anguo Huang

There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).

Apparatus and method for forward error correction over a communication channel

Flexible rate communication signalling apparatus and methods are disclosed. A determination is made as to a set of one or more of first frames and second frames which would provide a desired communication rate. The first frames and the second frames have a common frame structure but different associated rates. The determined set of one or more of the first frames and the second frames, including received client signals, is generated.

Flexible rate communication signalling

Provided is an apparatus and method for transmitting data over a communication channel having at least one physical lane for transmitting data. The apparatus includes, for each physical lane, allocation circuitry configured for allocating data in logical lanes corresponding to the physical lane. The apparatus also includes, for each physical lane, a multiplexer configured for bit-interleaving the data from the logical lanes corresponding to the physical lane into interleaved data for transmission over the physical lane. In accordance with an embodiment of the present disclosure, for each physical lane, the allocation circuitry is configured for allocating the data such that the interleaved data for transmission over the physical lane has clusters of sequential bits of the same symbol. Thus, upon transmission and reception by a receiver, any correlated errors affecting sequential bits may affect fewer symbols. Also provided is an apparatus and method for receiving data in a complementary manner.

Apparatus and method for communicating data over a communication channel

Despite a recent revision, IEEE 1588&#x2122;-2008 does not provide a complete implementation for PTP (precision time protocol) that accounts for variable delays introduced by network components. According to a broad aspect, the present disclosure provides implementations that account for variable delays introduced by network components. Therefore, the amount of time that a packet spends in transit through a transparent clock can be accounted for. According to another broad aspect, there is provided a master-slave mode that allows a transparent clock to function as a master or a slave to another clock.

System and method for accounting for time that a packet spends in transit through a transparent clock

There are disclosed systems and methods for reducing the average delay and the average delay variation of network communication data in a buffer. The buffer comprises a plurality of memory entries, and associated with the buffer is a read point and a write pointer. The buffer has a depth defined as the number of memory entries in the buffer between the memory entry pointed to by the read pointer and the memory entry pointed to by the write pointer. In one embodiment, at least one of the read pointer and the write pointer is initially set to establish the depth of the buffer to be a first value. The variation of the depth of the buffer is then monitored for a predetermined period of time as network communication data flows through the buffer. The depth of the buffer is then reduced based upon this monitoring.

Reducing delay and delay variation in a buffer in network communications

Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.

Signal format conversion apparatus and methods

A method of manufacture a transport network system includes: receiving input data having an input encoding; generating encoded data, having a transcode encoding, from the input data; generating an error correction redundancy for the encoded data; and sending an output frame, having the encoded data and the error correction redundancy, for increasing a net coding gain of the output frame based on the transcode encoding and the error correction redundancy.

Transport network system with transparent transport and method of operation thereof

A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises interleaving data in a predetermined format and controlling distribution of the data irrespective of the format received such that the data can be processed at the destination and passed to downstream components.

Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads

A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.

Transporting stream client signals via packet interface using GFP mapping

In a communication system that uses virtually concatenated payloads, techniques to determine when to declare and when to clear alarm indication signal (AIS) for a group. The declaration of AIS for a group may occur based on when declaration of AIS for a member of a group occurs. The clearing of group AIS may occur based on when clearing of AIS by a last member of a group to clear AIS occurs.

Techniques for group alarm indication signal generation and clearing

A device for mapping and demapping cells in an orderly manner is provided. The device employs a channel identifier and in certain configurations a buffer and series of stages to provide for relatively ordered, predictable mapping and demapping of data, such as virtual concatenation data.

Control mechanism for mapping cells and packets

A method and apparatus for determining a read address for received data in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise determining a minimum write address using a plurality of memory elements and using the minimum write address in connection with received read addresses to determine group read addresses.

Method and apparatus differential delay compensation processing of virtually concatenated data

A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.

Enhanced SDRAM bandwidth usage and memory management for TDM traffic

Frames of data comprised of frameword bytes and a payload are processed by identifying a start of a first frame and a phase of the first frame concurrently based on the frameword bytes, and aligning data in a second frame, based on the phase of the first frame, to make a start of the second frame coincide with a start of a byte boundary.

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San Francisco, CA, United States of America

Jean-Michel Caia