Bull S.a.

Bull Sas

Jean-Marie Boudry

Sleiman N Chamoun

Marcelo Duhalde

Jacques Brinkuysen

A method and a device is disclosed for encoding/decoding digital data transmitted through a serial link, particularly of the so-called &ldquo;8B/10B&rdquo; type. A full encoded binary word includes 8 data bits and a 2-bit label. The logical state of a center bit triplet of the byte is detected. When all of the bits are in the same logical state, the center bit of the triplet is inverted prior to transmission. Otherwise, the byte is transmitted as is. The label is forced to the logical configuration &ldquo;10&rdquo; when there is a bit inversion, and to &ldquo;01&rdquo; in the opposite case. Upon decoding, this configuration is tested and the center bit received is selectively inverted as a function of the result of the test. In a preferred variant, the method also includes tests of the label and the triplet after decoding, when there has been a bit inversion in the encoding. The device comprises logical circuits based on inverters and &ldquo;AND,&rdquo; &ldquo;OR&rdquo; and &ldquo;EXCLUSIVE-OR&rdquo; logic gates.

Method for encoding/decoding digital data transmitted through a serial link, particularly of the 8B/10 type, and device for implementing same

An edge multiplier circuit comprises a chain of N phase-looped delay cells ( ). An order of cells to be delayed is determined by action loops. A first action loop ( ) is utilized for values of j varying from 1 to N, each corresponding to a total delay equal to j times an elementary delay (T ) of a cell. The delay is applied to the chain of N delay cells. An action of the first loop comprises a second action loop ( ) for values of i varying from 1 to N, each corresponding to a rank of a cell in said chain. An action of the second loop calculates a delay error (a (j, i)) output from the cell of rank i relative to an ideal delay that distributes the total delay of the chain equally to each cell. A first value of the error is calculated prior to activating an additional elementary delay (T ) of the cell of rank i and a second value of the error is calculated if the first value is higher than a predetermined threshold, after activating an additional elementary delay of said cell of rank i. The rank i in this case completes the order to be determined.

Edge multiplier circuit

The present invention relates to a bidirectional two-way CMOS link of the type including a tailored transmission line (AB) connecting two integrated circuits to its two ends. The integrated circuits respectively including a transceiver that includes a transmitter stage ( ) and a receiver stage ( ), interfacing with the transmission line (AB) and controlled to transmit or receive digital data exchanged over the transmission line (AB) as a function of a control signal (transmission_gd) to put it in either the transmission mode or the reception mode, the transceivers never being in the same mode at the same time. The link is characterized in that each transceiver includes at least one PMOS transistor (MA), and one (NMOS) transistor (MB), which are controlled respectively by the control signal and are dimensioned and arranged to adapt the link to the two ends of the transmission line (AB). The invention in particular is utilized in tailoring of links that connect processors of a multiprocessor platform.

Bidirectional two-way CMOS link tailored for reception and transmission

A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term 'hysteresis' as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.

Variable delay cell with hysteresis and ring oscillator using same

The integrated circuit includes at least one conductance (6) which is adjustable by a digital control signal (17) which encodes steps in value for quantizing an exact value to within a fixed relative accuracy .DELTA.p. The conductance (6) includes elementary conductances which each define a step in value such that each elementary conductance is dimensioned so that a single level in value of the conductance (6) corresponds to two successive levels of the value of the digital control signal (17). If the result from the first of the two levels of value of the digital control signal (17) is a value which is lower, or respectively higher, than the exact value, the corresponding elementary conductance is enabled, or respectively disabled. Accordingly, the adjusted total value of the conductance (6) is equal to the exact value to within the same relative accuracy .DELTA.p, without oscillating between two values straddling this exact value. It is possible to use this type of conductance in high frequency communication integrated circuits.

Integrated curcuit with conductance adjustable by digital control signal

The invention relates to the field of rapid switching input-output couplers for high rate data transfer buses. The input-output coupler of an integrated circuit enables signals to be exchanged with identical couplers disposed in other integrated circuits by means of a bus line (51). Such a coupler comprises a transmitter (6) and a receiver (7) connected to a line (51) by a first conductor (5). The transmitter (6) comprises a first switch (63) whose on condition puts the first conductor (5) at a potential Vb. The coupler comprises additionally a second switch (64) or (65) whose on condition switches the first conductor (5) to a potential Vtt and arranged such that the switching on of the second switch is only possible after the switching off of the first switch (63). Accordingly, rapid switching on of the second switch (64) or (65), enables rapid variations to be obtained between two discrete states of potential Vb and Vtt of the electrical conductor connecting the transmitter to the bus line, with high stability in each of these two states.

Rapid switching input-output couplers for high rate data transfer buses

A process and apparatus for adjusting clock signals in a synchronous system of the type having several units synchronized by clock signals furnished by at least one generator providing a basic clock signal The generator includes means for adjusting the clock signals, the adjustment means being controlled by digital adjustment parameters.

Process and device for adjusting clock signals in a synchronous system

A time constant circuit for regulating the phases of clock signals of a synchronous system includes a plurality of transfer gates composed of MOS-type transistors whose drain-source leads constitute resistance elements. The time constant is adjusted by selectively activating transfer gates, the capacitance of the circuit being the total structural capacitance of the MOS transistors. To ensure that the capacitance remains constant, each transfer gate is associated with an auxiliary compensating circuit which, when activated, introduces a capacitance of the same value as the capacitance of the gate in the conducting state. The invention likewise relates to a variable-delay circuit using the time constant circuit.

Growing community of inventors

Beynes, France

Jean-Marie Boudry