International Business Machines Corporation

Integrated Device Technology, Inc.

Maxim Integrated Products, Inc.

Analog Devices,inc.

The Whitaker Corporation

Jean-Marc Roger Mourant

James Francis Imbornone

Feng-Jung Huang

Shawn Bawell

Chuying Mao

Daniel Shkap

Ran Li

Olivier Hubert

Gregory Szczeszynski

Naveen Krishna Yanduru

Kathiravan Krishnamurthi

Tao Liang

John Frank Scampini

Scott Munro

Yang Qian

Peter Bacon

Mehdy Abdollahian

Ron Gatzke

Gregory Krzystof Szczeszynski

Holly A LaFerrara

Chris Stephens

Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Multi-bit cell attenuator

Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2&#xd7;LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2&#xd7;LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.

Circuits and systems for wideband quadrature signal generation

Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.

Reduced VSWR switching

A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Constant impedance switch

Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition. Integration of configurability and/or control may reduce complexity in design, development, control, optimization, production and application, e.g., by eliminating interfaces, mismatches or excessive capacitance between discrete chips.

Phase, amplitude and gate-bias optimizer for Doherty amplifier

Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.

Low noise variable gain amplifier utilizing variable feedback techniques with constant input/output impedance

Hybrid-coding for improving transient switch response in a multi-cell programmable apparatus

An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IPperformance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IPof 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IPof 46 dBm and sustained at or above 40 dBm over a wide frequency range.

Matched feedback amplifier with improved linearity

A variable gain amplifier may include a gain block, a voltage control block, and a unity gain buffer block. The gain block may include a plurality of amplifiers having a fixed gain. The voltage control block is coupled to the output of the gain block. Moreover, the voltage control block controls, based on control voltages applied to the plurality of amplifiers having fixed gain, current output by the plurality of amplifiers. The unity gain buffer amplifier is coupled to receive the current output by the plurality of amplifiers of the voltage control block. The unity gain buffer amplifier provides an output signal of the variable gain amplifier. Related systems, methods, and articles are also described.

Low noise variable gain amplifier

Analog beamformers for continuous wave ultrasonic receivers, typically realized in integrated circuit form and using a direct quadrature baseband conversion architecture for CW Doppler to eliminate a second down conversion mixer and second synthesizer. The beamformers use integrated mixers and LO's for phase steering, and dedicated ring counters for each channel for lower noise. Input filtering may be provided with switchable RF input low pass filters. The integrated circuit includes the ultrasound signal VGA and beamformer on the same chip. An auxiliary channel may be included for a self-test mode. Also a programmable bit soft shutdown feature, programmable via the serial port, allows disabling individual channels. Various other features are disclosed including cascading of multiple integrated circuits for a much greater number of channels.

Analog beamformers for continuous wave ultrasonic receivers

Analog control integrated FET based variable resistors and attenuators using the variable resistors having a wide range of monotonic and substantially linear attenuation with control voltage for use in circuits having AC signals of AC signal frequencies. The variable resistors comprise field effect devices (FETs) biased to operate in their linear region and having their bodies and gates coupled to a reference voltage and a control voltage, respectively, through impedances, typically resistors, having impedances that are higher than the impedances of parasitic capacitances at the signal frequencies. This allows the body and gate of each FET to vary in voltage with the signal to maintain the bias of the FETs in the presence of large signals. Various embodiments are disclosed.

Analog control integrated FET based variable attenuators

RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and at least one region of a second conductivity type in the body, with a conductive layer over at least part of the body and the region of the second conductivity type and insulated therefrom. The MOS device may be coupled into a phase distortion circuit individually or in back-to-back pairs and biased to invert the body under the conductive layer for small signal amplitudes and not for large signal amplitudes, or to not invert the body under the conductive layer for small signal amplitudes and to invert the body under the conductive layer for large signal amplitudes. Various embodiments are disclosed.

Phase distortion using MOS nonlinear capacitance

An image trap filter disposed between the low noise amplifier and the mixer of a radio frequency receiver that overcomes the adverse effect of process variations on image signal rejection for both a single-band radio frequency receiver and a multi-band radio frequency receiver by setting the image trap filter response at the center of the band of interest at production test. The image signal problem is presented at the input of the radio frequency receiver and the image trap filter is adjusted for the desired frequency response.

Growing community of inventors

Groton, MA, United States of America

Jean-Marc Roger Mourant