Texas Instruments Corporation

Jean-Marc Philippe Bachot

Eric L Badi

Gilbert Laurenti

Douglas E Deao

Mark L Buser

Jean-Pierre Giacalone

Shigeshi Abiko

Marc Couvrat

Armelle Laine

Herve Catan

Karim Djafarian

Vincent Gillet

Alain Boyadjian

Gael Clave

Anne Lombardot

Francois Theodorou

Yves Masse

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Laurent Ichard

Emmanuel Ego

Frederic Nidegger

David Russell

N M Ganesh

An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper () incorporating self-timing logic () and a mux () is used to couple a single access memory core () to a memory interface unit (). The memory interface unit () couples a central processing unit () to the memory wrapper (). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle. In accordance with another aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) (). In another embodiment of the invention, a memory core (embodied within RAM) incorporating the self-timing architecture is incorporated directly into the processor core thereby avoiding the need for a memory wrapper and the time delay associated with passing information from the processor core via the memory interface unit and to the memory core. Direct incorporation of a memory core into the processor core facilitates more intensive accessing and additional power savings. In accordance with yet another aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) () is further incorporated into an electronic computing system, such as a digital cellular telephone handset ().

Method and apparatus for accessing a memory core multiple times in a single clock cycle

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper ( ) incorporating self-timing logic ( ) and a mux ( ) is used to couple a single access memory core ( ) to a memory interface unit ( ). The memory interface unit ( ) couples a central processing unit ( ) to the memory wrapper ( ). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle. In accordance with another aspect of the invention, the apparatus and method for using self-timing logic to make at, least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP) ( ). In another embodiment of the invention, a memory core ( embodied within RAM 206) incorporating the self-timing architecture is incorporated directly into the processor core thereby avoiding the need for a memory wrapper and the time delay associated with passing information from the processor core via the memory interface unit and to the memory core. Direct incorporation of a memory core into the processor core facilitates more intensive accessing and additional power savings.In accordance with yet another aspect of the invention, the apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is incorporated into a data processing system, such as a digital signal processor (DSP)( ) is further incorporated into an electronic computing system, such as a digital cellular telephone handset ( ).

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Plascassier, France

Jean-Marc Philippe Bachot