Csem Centre Suisse D'electronique Et De Microtechnique Sa

Centre Suisse D'electronique Et De Microtechnique Sa

Csem Centre Suisse D'electronique Et De Microtechnique Sa&#x2014;recherche Et D&#xe9;veloppement

Csem-centre Suisse D'electronique Et De Microtechnique

Jean-Marc Masgonty

Christian Piguet

Claude Arm

Stefan Cserveny

Flavio Rampogna

Pierre-David Pfister

Philippe Vuilleumier

Fr&eacute;d&eacute;ric Robin

A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

System for producing addresses for a digital signal processor

A neural network having layers of neurons divided into sublayers of neurons. The values of target neurons in one layer are calculated from sublayers of source neurons in a second underlying layer. It is therefore always possible to use for this calculation the same group of weights to be multiplied by respective source neurons related thereto and situated in the underlying layer of the neural network.

Method and a system for calculating the values of the neurons of a neural network

A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate. The memory includes read/write control circuits which apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read. Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where &ldquo;Sel&rdquo; is a cell selection signal representative of the address, &ldquo;W&rdquo; is a write command, {overscore (W)} is a read command, &ldquo;D&rdquo; is the data to be written into the addressed cell and &ldquo;.&rdquo; indicates the AND function.

Random access memory

A D-type master-slave flip-flop includes a master unit receiving an input variable and producing two first intermediate variables, a transfer unit including at least two logic gates and a clock connection connected to one input of each of the gates, which are adapted to supply two second intermediate variables as a function of the input variable and the clock signal and are looped to the master unit, and a slave unit to form at least one output variable. Another input of a first gate of the transfer unit is connected to the master unit to receive directly the true value of one of the variables supplied by the master unit. Another input of the second gate of the transfer unit is connected to the master unit to receive therefrom the complement of the same variable. The second intermediate variables are independent of each other. The flip-flop has the advantage that it is insensitive to the slopes of the flanks of the clock signals.

D-type master-slave flip-flop

The disclosure relates to microprocessors and, more particularly, to a system for organizing and a method for the sequencing of the circuits of a microprocessor. The instruction registers are connected in chains and an inhibiting device is associated with each instruction register. Each inhibiting device has its inputs connected to the inputs of the associated register and to the clock circuit a provides and signal for the loading of the associated instruction register when it detects a predetermined combination of digits in the associated register.

Microprocessor instruction pipeline having inhibit logic at each stage

In this device, each processor (P1 to P3) is associated with at least one dressable space (R1 to R3), whereas all the processors and all the addressable spaces are in communication by way of a common communication bus (BC). Between all the processors and each addressable space is connected an intercommunicating connection node (N1 to N3), each connection node including control means (LC, D1, D2) for

System for information processing comprising plurality of processors

The invention relates to computer systems containing at least one microprocessor associated with at least one memory in which are recorded instructions of a program and/or data to be processed according to the instructions. The memory is divided up into N=2 modules, one of which has a greater capacity than the other and the access time of which increases in proportion to its capacity. The module of smallest capacity is reserved for the instructions and/or data of the programs which are the most often used and the module of larger capacity is reserved for the instructions and/or data of the programs which are the least often used. The instruction contains a code identifying the module to be used.

Hierarchical ROMs that are selectively accessed by microprocessor

A memory element includes a master flip-flop (1) intended to control a slave flip-flop (2) via a transfer variable (A). The slave flip-flop (2) consists of a first gate (2a) controlled by the transfer variable (A), a clock signal (CK) and a true output variable (Q), so as to deliver a complementary output variable (NQ), and a second gate (2b) controlled by the complementary output variable (NQ) and delivering the true output variable (Q). The master flip-flop (1) includes a first gate (1a) controlled by an input variable (D), the clock signal (CK) and a third variable which is formed by the transfer variable (A). The master flip-flop (1) also includes a second gate (1b) controlled by the output (B) from the first gate (1a) of the master flip-flop (1) and delivering the transfer variable (A). The first gate (2a) of slave flip-flop (2) includes, in order to accomplish the transfer of the input signal, only seven transistors at most.

Memory element of the master-slave flip-flop type, constructed by CMOS

It comprises first (3) and second (4) transmission logic gates each fed with one input variable. The first gate (3) applies a first elementary logic function (NAND) to one of the input variables and to a multiplexer control logic variable (S). The second gate applies, on the one hand, a second elementary logic function (OR) to the other input variable (I.sub.0) and to the same control variable (S) and, on the other hand, the first logic function (NAND) to the output (B) of the first gate (3) and to the result of the application of the second logic function (OR), in order to make up the output variable (Q, Q) of the multiplexer.

Growing community of inventors

Marin, Switzerland

Jean-Marc Masgonty