Siemens Aktiengesellschaft

International Business Machines Corporation

Infineon Technologies North America Corp.

Other

Jean-Marc Dortu

Albert Manhee Chu

Toshiaki Kirihata

Paul-Werner Von Basse

Karl-Peter Pfefferl

Ulrich Schaper

Dieter Kohlert

Andrea Herlitzek

Garbiel Daniel

John Atkinson Fifield

Frank David Ferraiolo

Christopher P Miller

Jason Edward Rotella

A delay locked loop circuit, in accordance with the invention, includes a delay line for providing a delay through the delay line in accordance with a control signal, the delay line being connected across an input node and an output node. A delay element is connected to the input node, the delay element for providing a predetermined delay value to an input signal from the input node to provide a delayed input signal. A phase comparator is connected to the output node and the delay element for comparing phase differences between an output signal and the delayed input signal and for outputting the control signal to the delay line such that the delay line provides the predetermined delay value to the delay line across the input and output nodes.

Delay element using a delay locked loop

A delay line, in accordance with the invention, includes a plurality of delay elements connecting an input and an output, the delay elements for causing a delay to be introduced to a signal passing through the delay elements. A voltage device is included for regulating power to the plurality of delay elements, the voltage device being adjustable to provide at least one predetermined voltage to the delay elements such that the delay in the delay elements is modified according to the predetermined voltage(s). The delay line may be employed in a delay locked loop, a clock circuit or other circuits.

Frequency range trimming for a delay line

A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

Delay-locked-loop (DLL) having symmetrical rising and falling clock edge

A clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock.

Clock latency compensation circuit for DDR timing

A calibrated Delay Locked Loop (DLL) arrangement synchronizes an output data signal thereof to an input clock signal. A delay line receives the input clock signal and generates a clock output signal having a selective delay. A gating circuit receives the clock output signal and separately generates an imitation data signal that corresponds to the clock output signal, and latches an input data signal with the output clock signal to generate an output data signal. The gating circuit is also responsive to a switching control signal having a first logical value for providing only the output data signal to an output thereof, and to the switching control signal having a second logical value for providing only the imitation data signal to an output thereof. A driver receives the gating circuit output signal and provides this signal as the calibrated DLL arrangement output data signal. A phase comparator in a feedback loop from the output of the driver is responsive to the switching control signal having the second logical value for comparing the input clock signal and the imitation data signal appearing at the driver output, and for causing the delay line to selectively synchronize the imitation data signal to the input clock signal. A switching control signal having the first logical value idles the phase comparator and maintains a latest delay introduced by the delay line.

Lock arrangement for a calibrated DLL in DDR SDRAM applications

A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

Variable domain redundancy replacement configuration for a memory device

A method of making a fault-tolerant memory device employing a variable domain redundancy replacement (VDRR) arrangement is described. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area, and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, redundancy units are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

Method of making a memory device fault tolerant using a variable domain

Power amplifier circuit for integrated digital circuits that combines the low permanent current consumption of a NOF push-pull output stage with the well-defined high level of a NON-NOFF amplifier stage having external clamp diode. An optimization of the leading edge is additionally achieved by fast drive and transient overdrive. A preceding inverter reduces the input capacitance of the overall circuit.

Power amplifier circuit for integrated digital circuits

Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs. In the address amplifier circuit the address is doubly stored and only those signals that cannot trigger a misdecoding are forwarded from the address amplifier to a decoder circuit.

Growing community of inventors

Munich, Germany

Jean-Marc Dortu