Stmicroelectronics (crolles 2) Sas

International Business Machines Corporation

Stmicroelectronics S.a.

Stmicroelectronics (grenoble 2) Sas

Jean-Marc Daveau

Philippe Roche

Michel Harrand

William Robert Lee

Sylvain Clerc

Subhrajit Bhattacharya

Didier Fuin

José Sanches

Thierry Lepley

Miguel Santana

Philippe Guillaume

Pierre Paulin

Reinaldo A Bergamashi/Rab

Marco Cornero

A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

Method for managing the operation of a test mode of a logic component with restoration of the pre-test state

A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Method for managing the operation of a circuit with triple modular redundancy and associated device

A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Signal processor executing variable size instructions using parallel memory banks that do not include any no-operation type codes, and corresponding method

Processes and arrangements for describing a system-on-chip at an abstract level. Contemplated is the creation of a &ldquo;virtual design&rdquo; and its automatic synthesis into a &ldquo;real design that includes IP blocks from a library as well as all required interconnections and interface logic between them. Significant reductions in the complexity, time and cost associated with system-on-chip designs can be enjoyed as a result.

Methods and arrangements for automatic synthesis of systems-on-chip

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Grenoble, France

Jean-Marc Daveau