Mentor Graphics Corporation

Siemens Industry Software Gmbh

Jean-Marc Brault

Hans Erich Multhaup

Nicolas Chaumont

Greg Bensinger

Charles W Selvidge

Jean-Paul Clavequin

Laurent Vuillemin

Each reconfigurable hardware modeling circuit of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a model computation subsystem configurable either to model elements of a circuit design, or to serve as a testbench element, or both, and a network subsystem comprising: network circuitry and signal reduction circuitry, the signal reduction circuitry configurable to perform a signal reduction function, the signal reduction function combining a plurality of status signals into a single status signal, the plurality of status signals comprising status signals received from one or more reconfigurable hardware modeling circuits in the plurality of reconfigurable hardware modeling circuits. Alternatively or additionally, each network circuit of a plurality of network circuits in the reconfigurable hardware modeling device may comprise signal reduction circuitry configurable to perform the signal reduction function.

Reduce/broadcast computation-enabled switching elements in an emulation network

Related communication signals between a simulator and an emulator are organized into logical channels. The signals in each channel are then be transmitted only as needed, reducing the use of the communication pathways between the simulator and the emulator. Further, the circuit components that will receive the communication signals to be shared on a channel are be physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to receive the signals sent by the simulator. Similarly, emulator components that send communication signals to be shared on a channel are physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to send these signals to the simulator.

Managing communication bandwidth in co-verification of circuit designs

According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

System and method of clocking an IP core during a debugging operation

Growing community of inventors

Guyancourt, France

Jean-Marc Brault