Secure-ic Sas

Institut Telecom/telecom Paristech

Other

Centre National De La Recherche Scientifique

Stmicroelectronics S.a.

France Telecom

Stmicroelectronics Asia Pacific Pte Limited

Group Des Ecoles Des Telecommunications

Orange

Institut Mines-telecom

Idemia Public Security France

Jean-Luc Danger

Sylvain Guilley

Philippe Nguyen

Thibault Porteboeuf

Lucas Hui

Benoît Miscopein

Adrien Facon

Florent Lozac'h

Jean-Michel Bard

Rachid Dafali

Robert Nguyen

Youssef Souissi

Thibaut Porteboeuf

Christophe Cunat

Philippe Hoogvorst

Sami Mekki

Florent Flament

Linda Guiga

A circuit for a Synthetic Physically Unclonable Function, acronym SPUF, in a computer device, wherein the circuit is configured to receive data from a plurality of hardware sensors and/or actuators accessible in the computer device; to determine deviations in the data; to determine a multivariate distribution of the deviations and to determine an identifier from the multivariate distribution. In described developments, deviations comprise random errors, statistical moments in data originating from sensors and/or actuators amongst accessible ones in the computer device can be selected, and entropy can be maximized. Computer program product embodiments are described.

Synthetic physically unclonable function

Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge. The system comprises:

Secret key generation using a high reliability physically unclonable function

Embodiments of the invention provide an electronic system for generating secret information comprising a Physically Unclonable Function (PUF) circuit, the PUF circuit being configured to provide a difference between two values of a physical variable of the PUF in response to a challenge applied to the PUF circuit. The system is configured to apply a set of challenges during an enrolment phase, and measure the physical variable difference provided by the PUF in response to each challenge. The system further comprises:

System and method for generating secret information using a high reliability physically unclonable function

There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.

Embedded test circuit for physically unclonable function

There is provided a method for testing a Physically Unclonable Function (PUF) implemented in a device, said PUF being configured to receive at least one challenge, each challenge comprising a set of bits, and to produce a set of responses, each response comprising at least one bit and corresponding to one challenge, said PUF comprising a circuitry including a set of PUF elements, each PUF element being controlled by at least one input bit corresponding to at least one bit of said challenge, wherein the method comprises the steps of:

Device and method for testing a physically unclonable function

There is disclosed a system for monitoring the security of a target system () with a circuit (), the target system () comprising at least one processor () and wherein: the circuit () comprises a finite-state machine () configured to receive data from one or more sensors () distributed in the target system (), at least one sensor () being located on the processor () of the target system (); the finite-state machine () is configured to determine a state output in response to data received from sensors (); the system monitoring the security based on said state output. Developments describe the use of a self-alarm mechanism comprising an encoder to encode states with redundancy, the application of an error correction code, comparisons with predefined valid encoded states, the triggering of an alarm to the processor, the determination of actions and/or retroactions on sensors and/or diagnostics and countermeasures.

Security supervision

The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in:

Circuit protection system and method

Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device () comprising a substrate () having a front surface () and a back surface (), the IC device further comprising a front side part () arranged on the front surface of the substrate () and stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface (). The system comprises an internal shield () arranged in a layer located below said data layer and a verification circuit configured to check the integrity of at least one portion of the internal shield.

System and method for protecting an integrated circuit (IC) device

The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit includes registers and logic gates, and a test thereof performs a differential power analysis on the registers of the circuit. A cryptography circuit being secure and including a first half-circuit associated with a second half-circuit operating in complementary logic, the electric power supply of the first half-circuit is separated from the electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test.

Method for testing cryptographic circuits, secured cryptographic circuit capable of being tested, and method for wiring such circuit

A cryptography circuit protected by masking, said circuit including means for encrypting binary words using at least one key k, means for applying linear processing operations and nonlinear processing operations to said words and means for masking said words. The binary words are unmasked upstream of the nonlinear processing operations by using a mask kand masked downstream of said processing operations by using a mask k, the masks kand kbeing chosen from a set of masks that is specific to each instance of the circuit.

Low-complexity electronic circuit protected by customized masking

In a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components, a first network of cells carrying out logic functions on the first component of said pairs, a second network of dual cells operating in complementary logic on the second component, the logic functions being carried out by each pair of cells in a pre-charge phase placing the variables in a known state on input to the cells and followed by an evaluation phase where a calculation is performed by the cells, the method includes detecting an anomaly by at least one non-consistent state.

Method for detecting abnormalities in a cryptographic circuit protected by differential logic, and circuit for implementing said method

A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary variables, including a first network of cells implementing logic functions on the first component of the pairs and a second network of dual cells operating in complementary logic on the second component of the pair. A calculation step includes a precharge phase, in which the variables are put into a known state at the output of the cells, and an evaluation phase in which a calculation is made by the cells. A phase of synchronizing the variables is inserted before the evaluation phase or the precharge phase in each cell capable of receiving several signals conveying input variables, the synchronization being carried out on the most delayed signal.

Method for protecting a programmable cryptography circuit, and circuit protected by said method

A method and apparatus are provided for sending pulses from a sender device to a receiver device in a transmission channel. The pulses represent information symbols, with each of these pulses being associated with a time slot in a symbol time. The method includes a training step that is carried out before sending payload information and that includes sending a training sequence made up of two parts. A first part of the training sequence includes at least one pulse of energy that is greater than the energy of a pulse carrying payload information. There are a large number of time slots between the sending of the pulse and the sending of the next pulse. A second part of the training sequence includes a set of pulses known in advance and similar to the pulses used for carrying payload information, the energy of each of these pulses being equivalent to the energy of a pulse carrying payload information.

Method for sending pulses in a transmission channel

A silicon integrated circuit includes a physically non-copyable function LPUF that generates a signature specific to the circuit. The function includes a ring oscillator composed of a loop traversed by a signal. The loop is formed of N topologically identical chains of lags connected in series and an inversion gate, a chain of lags being composed of M delay elements connected in series. The function also includes a control module generating N control words being used to configure the value of the delays introduced by the chains of lags on the signal traversing them. A measurement module measures the frequency of the signal at the output of the last chain of lags after updating the control words, and the control module can deduce from the frequency measurements the bits making up the signature of the circuit. A method and a system for testing such circuits are also provided.

Integrated silicon circuit comprising a physicallly non-reproducible function, and method and system for testing such a circuit

A cryptography circuit protected against observation attacks comprises at least one register R providing a variable x masked by the mask m, the masked variable being encrypted by a first substitution box S -in a cyclic manner. The circuit also comprises a mask register M delivering at each cycle a mask m, the transformation of m, the mask m being extracted from mbefore being encrypted by a second substitution box S', the new mask m&#x2032; obtained on output from this box S&#x2032; is transformed into a mask m&#x2032;before being stored in the mask register M. The transformation consists of a bijection or a composition law making it possible to reduce or indeed to cancel any high-order attack in accordance with a model of activity of the registers R and M. Cryptography circuits are protected against high-order observation attacks on installations based on masking.

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Antony, France

Jean-Luc Danger