Sgs-thomson Microelectronics S.a.

Jean-Louis Bernet

Claude Athenes

Jean-Bernard Saxod

A process for converting a first flow of data words supplied at the rate of a first clock into a second flow of data words comprising, inside the successive frames, a sequence of n data words of the first flow and accompanying data, the duration of each frame of the second flow being equal to the duration of n data words in the first flow. Said process comprises: storing the successive data words of the first flow in an input register (1); as soon as the register is full, writing its content in one of p intermediate registers (A, B, C); sequentially reading the p intermediate registers in an output register (5); and if, during a frame, the writing and reading sequence in the intermediate registers is such that an intermediate register is read while its writing has not been modified, skipping, at the beginning of the following frame, one reading order until one obtains an adequate synchronization which will then be maintained during the subsequent frames.

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LaBuisse, France

Jean-Louis Bernet