Stmicroelectronics S.a.

Freescale Semiconductor,inc.

Stmicroelectronics Gmbh

Jean Lasseuguette

Richard P Fournel

Cyrille Dray

Sébastien Barasinski

Christophe Frey

Thomas Andre

Philippe Candelier

Olivier Tico

Brad John Garni

Thierry Robin

Jérôme Casters

Stéphane Ollitrault

An apparatus for sensing current of a vehicle battery employs an extended counting analog-to-digital conversion process () to a chopped and amplified voltage appearing across a low ohmic shunt resistor () placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier () by matching the gain to the dynamic range of the ADC () permits a high dynamic signal sensing.

Apparatus and method for monitoring electrical current

A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal.

Memory circuit with sense amplifier

The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

Device for setting up a write current in an MRAM type memory and memory comprising

The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.

Low-voltage reading device in particular for MRAM memory

A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Magnetic random access memory array having bit/word lines for shared write select and read operations

A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (and) configured as a flip-flop for storing one bit. Each inverter includes a transistor (or) of a first type and a transistor (or) of a second type. The concentration of carriers in the conduction channel of the transistor () of the first type of one of the inverters () is different from the concentration of carriers in the conduction channel of the transistor () of the first type of the other inverter () so that the inverters have different threshold voltages.

Pre-written volatile memory cell

A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Growing community of inventors

Grenoble, France

Jean Lasseuguette