International Business Machines Corporation

Cisco Technology, Inc.

Jean L Calvignac

Fabrice Jean Verplanken

Daniel Orsatti

Claude Basso

Bernard J Naudin

Gilles Toubol

Pierre Secondo

Jean-Marie L Munier

Dominique Rigal

Ange Aznar

Jean-Pierre Lips

Claude R Galand

Didier F Giroir

Gerard Barucchi

Jean-Luc Frenoy

Bernard Brezzo

Pierre Vachee

Pierre J Huon

Jean-Claude Zunino

Michel Bouillot

Jean-Louis Picard

Rene R Castel

Jacques Feraud

Eric Saint-Georges

Mohamed Badaoui

Andre G Tracol

Christian Garcia

Andre Masclet

Guy Carle

Michel Dauphin

Luc Torres

Raymond Lenoir

Edward Stanely Suffern

Kenneth James Barker

Gerald Lebizay

Rene Gallezot

Maurice Duault

Claude Pin

Jean-Paul Aldebert

Victor Spagnol

Andre Pauporte

Philippe Klein

Denis Chevalier

Francois Kermarec

Daniel Mauduit

Jean Claude Dispensa

Pierre Austruy

Jean M Munier

Mathieu Michel Girard

Philippe Cuny

Yves Granger

Jean-Marc Millet

George M Calhoun

Charles Pierre Rheinart

Richard Dambricourt

Yves J Huchet

Haissam Alaiwan

Michel Susini

Richard H Waller

Oliver M Maurel

Tan T Pham

Jeane-Paul Aldebert

Jean-Pierre Sanche

Jacques M Clement Feraud

Jose Galcera

Eric Saint Georges

Francois Nicolas

Jacques-Louis Combes

Eric Saint-George

Jean-Claude Bigey

Jean-Christophe Debos

Philippe Jachimcsyk

Ruggero Ulivastro

Paul Chemla

A method for shaping network traffic in a computer network is described for packet data networks. The method includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.

Network traffic shaping

A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full. Finally, an output scheduler repeatedly selects for each output one of the crosspoint buffers corresponding to the output and the switch is responsive to the output scheduler to complete the transmission through the switch fabric of the data packet stored in the crosspoint buffer selected by the output scheduler.

Data switch

Traffic shaping apparatus is described for packet data communications networks, such as Asynchronous Transfer Mode (ATM) networks. The apparatus includes one or more packet queues for traffic having a plurality of different desired packet transfer rates, each queue being assigned to a connection having a predetermined desired packet transfer rate. Each incoming data packet is directed to the appropriate queue. Each of a plurality of timing circuits operate at a different frequency in a series of frequencies. The frequencies are selected so that the desired packet transfer rate for a connection can be established by summing outputs from more than one of the timing circuits.

Data communications

An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.

Method and device of multicasting data in a communications system

The invention discloses a method and an apparatus for use in high speed networks such as Asynchronous Transfer Mode (ATM) networks providing support for processing multipriority data flows at media speed, the major constraint being to share the storage and the ALU between all the tasks. The invention consists first in grouping the tasks in processes and the processes in set of processes all organized in decreasing order of their priority ; `on the fly`interruption of a lower priority process/set of processes by a higher priority process/set of processes is possible as well as reuse of the shared resources during task void states inactive in a process or between processes. In the preferred embodiment of the invention, the support of the reserved bandwidth and non reserved bandwidth ATM services data flows requires two different groups of processes, the highest priority being for the group of processes serving the reserved bandwidth service. With the principle of the invention when used in network equipment the media speed is sustained and many different network traffics can be simultaneously supported. The apparatus implementing the solution of the invention, allowing sharing of resources saves place and costa by the improved reduced number of sophisticated hardware components such as static memories and programmable logic circuits.

Method and apparatus to share resources while processing multiple

The method and apparatus of the present invention solve the problem of scheduling the transmission of cells in packet switched networks having network connections requiring a minimum bandwidth at connection establishment. The method and the apparatus further support any mixed traffic flow including connections requiring a minimum bandwidth, a fixed reserved bandwidth or no bandwidth at connection establishment. Scheduling is controlled by a dual scheduling mechanism having a first scheduler, triggered by absolute time, for scheduling the minimum service connections up to a rate corresponding to their reserved minimum bandwidth, a second scheduler and a queue of minimum service connection identifiers for communication between the two scheduling schemes. With the dual scheduling mechanism of the present invention, the minimum bandwidth for connections reserving a minimum bandwidth at connection establishment is guaranteed in each point of the connection path and at any time, with the level of fairness of the scheduling of the remaining bandwidth depending on the quality of the second scheduler.

Scheduling method and apparatus for supporting ATM connections having a

The invention discloses a method and an apparatus for implementing the physical interface in a network element connected to a packet network such as Asynchronous Transfer Mode (ATM) network. With the solution of the invention, the physical interface functions can be integrated on one chip for more than one network port. The physical interface is provided between port bit streams at media speed and word data flow transferred onto/from a bus which is under the control of the network equipment. The solution of the invention includes grouping logics and storage elements by islands of more than one port. Furthermore, the logics and storage elements for statistical counting operations can be grouped for a processing generalized to all ports. Finally, the solution of the present invention takes into account two characteristics of the physical interface which are the different rates between network link media speed and bus access rate and the technology of the high density static imbedded RAMs used for hardware integration. The Flip/Flop pointer RAMs of Flip/Flop data RAMs are duplicated and some interface RAMs are created to transfer control data between the islands and the generalized processing logical blocks.

Method and apparatus providing a multiport physical interface to high

The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.

Method and system for in-site and on-line reprogramming of hardware

A communication system comprises a plurality of nodes interconnected by links comprising a plurality of connections. The traffic between the nodes is set up by a reserved bandwidth service and/or a non reserved bandwidth service. The non reserved bandwidth service is controlled by a hop by hop backpressure mechanism. When the traffic entering a node exceeds a high threshold, the backpressure mechanism generates stop backpressure primitives in order to throttle the entering traffic. In case of congestion the mechanism is either able to selectively interuppt the connection contributing to the congestion without affecting the rest of the link traffic, or to globally stop all link traffic. Traffic can be resumed if traffic rates fall below the low threshold values.

Hop-by-hop flow control in an ATM network

An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.

Method and apparatus for priority level queueing in processing ATM cell

A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.

Efficient hardware/software interface for a data switch

A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46). The switch and other concentration logic receive a hub local clock (412). Isochronous traffic interchanges with the hub backplane through leads 410 and 411; between ports or between ports and the hub through leads 407 and 409. Data to a connected station is output (408) from port transmit interface (44). Differential Manchester encoded data are received (400) along with Token-Ring clock (401). Control signals are input (403). Isochronous data are received (409). Token-Ring packet Differential Manchester encoded data are finally output from the concentration logic (41).

Hub and interface for isochronous token ring

A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.

ATM cell multicasting method and apparatus

A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.

Multiplexed TC sublayer for ATM switch

The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.

ATM cell forwarding and label swapping method and apparatus

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LaGaude, France

Jean L Calvignac