Bull Sas

Bull S.a.

Jean-Jacques Pairault

Philippe Couvee

Zoltan Menyhart

Lionel Coutancier

Sylvain Jeaugey

Jacques Abily

Saïd Derradji

Elodie Marquina

Jean Perraudeau

Angelo Solinas

Guy Magnaud

Jordan Chicheportiche

Pierre Bacot

A computer device with synchronization barrier including a memory and a processing unit capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, the blocks being associated by groups in successive work steps. The device further includes a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Physical manager of synchronization barrier between multiple processes

An AMB component and a connection interface for a memory installation with fully buffered Dimm memory modules connected in series. The AMB component is disposed on a connecting line from memory modules to a memory controller of the memory installation to re-amplify the connecting line between two consecutive FBD memory modules. The connection interface includes an AMB amplifier component for the connection of a main memory card that includes at least one processor, to an auxiliary memory card of the type having a series of memory modules. Two series of FBD memory modules are connected to respective FBD channels in the auxiliary memory card using FBD connectors in a daisy-chain arrangement.

Card design with fully buffered memory modules and the use of a chip between two consecutive modules

The invention concerns the use of an AMB component () in a memory installation with fully buffered Dimm memory modules connected in series, characterised in that the AMB component () is placed on a connecting line () from the memory modules () to a memory controller () of the installation in order to re-amplify the connecting line () between two consecutive FBD memory modules (). The invention also concerns a connection interface that includes such an AMB amplifier component () for the connection of a maincard () that includes at least one processor, to an auxiliary memory card of the type with a series of memory modules (), where the maincard has at least one pair of channels connected to the processor. Two series of FBD memory modules () are connected to respective FBD channels in the auxiliary memory card using FBD connectors () in a daisy-chain arrangement.

A connection arrangement for a mainboard having at least one memory card connected to a processor and two series of FBD memory modules connected to respective FBD channels in the memory card by means of FBD connectors using a daisy-chain arrangement. Each channel of the memory card is connected to a linking module to another card the linking module receives two separate FBD channels and includes a FBD type connector with two series of electrical contact pins respectively connected to two paired channels of the memory card. The FBD connector is mounted on the back of the memory card so as to be associated with a connection interface providing the connection to a mainboard. The mainboard is also equipped with a connector of the FBD type designed for inter-card connection.

Interface connection device for connecting a mainboard to a memory card having two series of memory modules

A Process for coherent management of exchanges between memories in an information system having at least two levels of memories. The information system in one embodiment is constituted by a central subsystem which can communicate with one or more peripheral subsystems by means of input-output units. The central subsystem includes several processors linked to a central memory and to the input-output units. Each processor includes an associated cache memory linked with the central memory. In operation, each processor executes the instructions of programs contained in an associated cache memory. If the cache memory does not contain the data necessary to the associated processor, the data is read in the central memory and a copy is made using memory blocks of predetermined size. The coherent management of exchange between memories is achieved by dynamically applying a management mode selected as a function of the use that is made of each block. The management mode, either update or invalidate mode, is switched based upon a predetermined threshold of ineffectiveness for a particular mode being reached. Furthermore, soft misses can be a criteria for the ineffectiveness of the invalidation mode.

Process and system for switching between an update and invalidate mode for each cache block

The invention relates to the field of data processing systems and provides a method and system to enable replacement of memory modules (MU.sub.i) connected to a bus (MB) without interrupting the functioning of the system, wherein for any writing request addressed to a module to be replaced (MU.sub.i), this writing request is executed simultaneously and at the same address by the module to be replaced (MU.sub.i) and by a replacement module (MU.sub.r), and for any reading request addressed to the module to be replaced (MU.sub.i), only the module to be replaced (MU.sub.i) is authorized to execute this reading request. Next, a recopying process is started which includes sending reading and rewriting requests to a set of addresses covering the entirety of the memory space of the module to be replaced (MU.sub.i).

Growing community of inventors

Boulogne-Billancourt, France

Jean-Jacques Pairault