Qualcomm Technologies, Inc.

Qualcomm Incorporated

Arteris, Inc.

Arteris S.a.

Jean-Jacques Lecler

Philippe Boucard

Laurent Rene Moll

Alain Artieri

Philippe Martin

Shyamkumar Thoziyoor

Boris Boutillier

Jonah Probell

Subbarao Palacharla

Samir Vijay Ginde

Rakesh Kumar Gupta

Kedar Bhole

Christophe Avoinne

Luc Montperrus

Sparsh Singhai

Gopi Tummala

Syed Minhaj Hassan

Christophe Jean-Luc Layer

Carlo Spitale

Luigi Vinci

Jonah Proujansky-Bell

Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

Dram-aware caching

Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.

Memory bank group interleaving

A method for dynamic memory scheduling with enhanced bank-group batching is described. The method includes determining a read-bank group-spread of each rank, as a number of bank-groups of each respective rank targeted by at least one read instruction. The method further includes determining a write-bank group-spread of each rank, as a number of bank-groups of each rank targeted by at least one write instruction. The method also includes stalling a current batch of read instructions in a rank when the read-bank group-spread of the rank is less than a predetermined value. The method further includes stalling a current batch of write instructions in a rank when the write-bank group-spread of the rank is less than the predetermined value.

Dynamic memory scheduling routine with enhanced bank-group batching

In certain aspects, a circuit for modulo-3 operation has an encoder stage coupled to a binary number, wherein the encoder stage includes one or more encoders, each one of the one or more encoders receives one or two binary bits of the binary number and generates a unary code of encoder. The circuit for modulo-3 operation further has one or more levels of reduction stage, wherein a first level of the one or more levels of reduction stage includes one or more mergers of first reduction, each one of the one or more mergers of first reduction receives two unary codes of encoder or a unary code of encoder and a bit from the binary number and generates a unary code of first reduction.

Method and apparatus for ternary mapping

Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.

Zero-latency network on chip (NoC)

A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.

Coherency controller with reduced data buffer

A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Adaptive tuning of snoops

A first frame and a second frame are combined into an extended frame. The extended frame is encapsulated and transmitted over a channel as an extended physical digital. A transmission error notification is received, indicating error in a reception of the transmitted extended physical digital. In response, a re-transmission encapsulates the first frame into a first physical digit, transmits the first physical digit over the channel, encapsulates the second frame into a second physical digit, and transmits the second physical digit over the channel.

Differential formatting between normal and retry data transmission

The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Network on a chip socket protocol

A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

DMA engine with STLB prefetch capabilities and tethered prefetching

A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

Three channel cache-coherency socket protocol

A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

System translation look-aside buffer with request-based allocation and prefetching

The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

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Antibes, France

Jean-Jacques Lecler