Stmicroelectronics (rousset) Sas

Stmicroelectronics (crolles 2) Sas

Jean-Jacques Fagot

Philippe Boivin

Olivier Weber

Emmanuel Petitprez

Franck Arnaud

Emeline Souchier

An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.

Co-integration of bulk and SOI transistors

A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

Method for producing transistors, in particular selection transistors for non-volatile memory, and corresponding device

Growing community of inventors

Rousset, France

Jean-Jacques Fagot