Lsi Corporation

Jean Jacob

Srinivasa Rao Kothamasu

Sathappan Palaniappan

Ravindra Bidnur

Dharmesh Kishor Tirthdasani

Debjit Roy Choudhury

Priya Gururaj Kulkarni

Sajith Kizhakke Kalathil Achuthan Kutty

A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Method and apparatus for power management control of an embedded memory having sleep and shutdown features

A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

Interconnect congestion reduction for memory-mapped peripherals

Growing community of inventors

Kerala, India

Jean Jacob