Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Jean-Francois Link

Mark Wallis

Joran Pantel

Vincent Onde

Dragos Davidescu

An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Programmable logic block with multiple types of programmable arrays and flexible clock selection

A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Input signal shaping for a programmable logic array

An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Programmable logic array with reliable timing

A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.

Digital-to-analog converter

A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.

Switch-mode power supply control

A system is provided for controlling access to protected data. The system includes storage means, protection means, an internal key, and means for receiving an input key from the outside. The storage means includes a protected zone for storing the protected data, and a command input for denying or authorising access to the protected data. The protection means controls access to the protected data by selectively activating the command input of the memory. The protection means authorises access to the protected data only when the internal key and the input key are identical. Also provided is a method for controlling access to protected data stored in a protected zone of a storage means. According to the method, an input key is received from the outside, and access to the protected data is authorised only when the input key and an internal are identical.

System and method for controlling access to protected data stored in a storage unit

An electronic device for storing protected data is disclosed. The electronic device includes memory protection logic operable to interface with memory, such as non-volatile ROM for storing protected data therein. The protected data in one embodiment is program code. The access to the protected data is restricted by a local processor, such as a microcontroller or microprocessor for execution thereon within the electronic device. Further, the electronic device includes validation logic operative in a first mode, for checking the validity of the data and for producing a validity signal, such as a checksum, enabled to determine whether that data is valid. In order to prevent access to intermediate validity calculations which may allow an individual to gain knowledge of the protected data, a validity signal output control is provided for inhibiting an output of the validity signal to outside the device until the validity of a predetermined quantity of the protected data has been checked. This predetermined quantity is made sufficiently large and preferably equal to all of the protected data. In another embodiment, a reset for setting the contents of the validity signal if the checking is interrupted is also included.

Growing community of inventors

Trets, France

Jean-Francois Link