Cadence Design Systems, Inc.

Pmc-sierra, Inc.

Microsemi Storage Solutions (u.s.), Inc.

Cadenee Design Systems, Inc.

Jean-Francois Delage

Guillaume Fortin

Louis-Francois Tanguay

Hormoz Djahanshahi

Mathieu Gagnon

Tiberiu Galambos

Rania Hassan Abdellatif Abdelrahim Mekky

Philippe Salib

Stephane Leclerc

David Michael Burnell

Bahar Youssefi

Zheng Lai

Embodiments included herein are directed towards a charge device model ('CDM') protection circuit. The circuit may include a power supply, a power clamp operatively connected to the power supply, at least one diode connected with the power clamp, a field effect transistor (“FET”) operatively connected with the at least one diode and a trigger mechanism configured to activate the FET.

Circuit and method for charge device model protection

A method and system for performing a duty cycle correction and quadrature error correction for a quarter-rate architecture TX/RX communication system, including correcting a duty cycle error between a first clock signal and a second clock signal, and correcting a quadrature error between a third clock signal and a fourth clock signal.

Digitally-controlled quadrature correction loop

Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.

Data sampler with capacitive digital-to-analog converter

Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.)

Quarter-rate data sampling with loop-unrolled decision feedback equalization

Various embodiments provide for data sampling with loop-unrolled decision feedback equalization. In particular, some embodiments provide for an unrolled first-tap Decision Feedback Equalizer (DFE) loop that comprises parallel data samplers that each include a tri-state output.

Data sampling with loop-unrolled decision feedback equalization

A system, method, and circuits for power efficient margining in a differential output driver that includes segments connected to outputs of the driver. Each segment can be configured independently to different states by activating corresponding transistor combinations. In a transmitting state, the transistors transmit data by establishing current paths between the driver outputs and a positive supply rail or a ground rail. In a margining state, the transistors are statically configured to form current paths that differ from those of the transmitting state, such that the segment contributes substantially a same differential impedance between the driver outputs as would be contributed by the segment when in the transmitting state, while contributing a different common mode impedance than in the transmitting state. The current paths of the margining state extend through transistors that transmit data in the transmitting state.

System and method for interchangeable transmission driver output stage and low-power margining mode

A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Method and apparatus for driving a laser diode

The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery ('CDR') loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock module is required, wherein determining includes determining two transitions in a sampling triplet. If it is determined that the fast-phase lock module is required, embodiments may include providing a trigger signal to the fast-phase lock module. Embodiments may further include receiving the trigger signal at the fast-phase lock module associated with the electronic circuit and performing a fast-phase lock operation on the signal.

System and method for saddle point locking detection during clock and data recovery

A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.

Variable-length digitally-controlled delay chain with interpolation-based tuning

A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Optionally, the programmable delay element utilizes current-mode logic (CML) and the control signal is a thermometer coded digital signal. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.

Growing community of inventors

Montreal, Canada

Jean-Francois Delage