Thomson-Csf

Thompson-Csf

Jean-Edgar Picquendar

Jean-Luc Berger

Roger Benoit-Gonin

Boris Sokoloff

Pham N Tung

Jean-Louis Coutures

Sylvain Fontanes

Daniel Forster

Pham Ngu Tung

Christian Auzet

The output filters of the modulator and of the demodulator, the input filter of the demodulator are transverse charge-transfer filter whose weighting coefficients are determined by the result of the division between the numerator and the denominator of the recursive charge-transfer filter having the desired passband characteristic, the number of the coefficients which the transverse filter comprises being limited.

Charge-transfer modulator-demodulator

The switched-capacitance amplifier comprises n capacitors C.sub.11 to C.sub.1n which are periodically switched in parallel and in series, the n parallel-switched capacitors being charged simultaneously by the same voltage V.sub.E. An amplified voltage n.times.V.sub.E is obtained between the end terminals A and B of the n series-switched capacitors. Periodic switching of the n capacitors in parallel and in series is performed by means of MOS transistors T.sub.11 to T.sub.1(2n-1) and T.sub.21 to T.sub.2(n-1) which operate in the switching mode. The n capacitors and the MOS transistors are integrated on the same semiconductor substrate.

Switched-capacitance amplifier, a switched-capacitance filter and a

An analog device for reading a quantity of electric charge, for example, in a transversal charge transfer filter. The device includes a capacitor and two MOS transistors which are connected in series to the point in the filter where the charge is to be read. The capacitor is connected to the common point of the two transistors which are controlled in phase opposition to insure charging of the capacitor. The capacitor maintains a potential at the charge reading point constant. Any variation in the quantity of charge under an electrode is converted into a variation of potential at the common point and this forms the read signal which is detected by means of a third MOS transistor.

Device for reading a quantity of electric charge

The invention relates to filters using a charge-transfer device as an active element it consists in providing such a filter with an output circuit of first order interpolator type; this circuit may be external to the charge-transfer device or partially integrated threwith by associating therewith an additional weighting cell and by using another set of weighting coefficients.

Sampling filter

Charge transfer filtering device which comprises a recursive filter and a non-recursive filter. The two filters on separate semiconductor substrates have charge injection means 12, 10 receiving the input signal E for the non-recursive filter 2 and the output signal S, previously phase-displaced by 180.degree. by means 9, for the recursive filter 1. Means 15, 16, common to both filters, ensure the reading and summation of the charge quantities weighted by means P and 14 and then the supply of the output signal S.

Charge transfer filtering device

A filter comprising a charge-coupled device having a first group of cells weighted according to a recurring filter law and having a second group of cells weighted according to a non recurring filter law. The cells of the first and second groups are interposed alternately and the displacement of the charges under these cells is carried at frequency twice that of the sampling rate of the input signal. Thus the effects of transfer inefficiency are suppressed without added hardware.

Apparatus for filtering an electrical signal with a charge-coupled device

The invention relates to hybrid filters comprising a recursive part and a non-recursive part which make it possible to synthesize the filter by splitting the desired pass-band into two. It consists in using for the design of such a filter a charge-coupled device (CCD) in which these two parts are directly linked by a simple charge transfer mechanism without any other connection.

Charged-coupled device filter

The present invention relates to telephony switching circuits which are used in electronic automatic exchanges operating on the time-division multiplex system known as PCM. According to the invention, a spatial and time switching circuit comprises a plurality of registers for memorizing the binary words of an input PCM frame, a plurality of time-slot registers for memorizing the output time-slots of the binary words, means for reading out the binary words registers when the time-slots defined by the time-slot registers occur, means for spatially switching the binary words thus readed out onto a plurality of output PCM links, and means for filling the output time-slots into the time-slot registers and selecting the output PCM links.

Telephone switching circuit

The invention relates to telephone transmission systems in which frequency multiplexing is carried out by digital processes. It consists in substituting to a computation step of an analytical signal a computation step of a much simpler complex signal. The ultimate signal obtained is not compatible with standard multiplexing apparatus, but may nevertheless be transmitted along ordinary channels.

Telephone transmission system comprising digitally processing frequency

The invention relates to machines by which it is possible to compute the discrete Fourier transform of a collection of N numbers in the case where N = 2.sup.n. The invention consists in using the properties of Pease's decomposition, according to which ##EQU1## and in constructing a computer comprising n identical modules except for the coefficients memorized therein, these modules each effecting the application of a term C.times.E.sub.m .times.P.

Computer for computing a discrete Fourier transform

A novel high-speed logic gate of compact design, having low energy consumption comprises a plurality of components each constituted by two complementary transistors and saturable resistors integrated upon one in the same substrate. The base of the first transistor has for its base a portion of the collector of a second transistor, and for its collector the base of the second transistor. The second transistor has its base diffused into its emitter into its base.

High-speed logic gate with two complementary transistors and saturable

A novel semiconductor store element comprises a bistable pnpn structure of the kind described in the copending Patent application Ser. No. 527,918, addressed by a structure of the same type. The system has an area of the order of 10 to 20 square microns and possesses a high switching speed.

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Paris, France

Jean-Edgar Picquendar