Sgs-Thomson Microelectronics S.a.

STMicroelectronics

Thomson Semiconducteurs

Stmicroelectronics (Rousset) Sas

Sgs-Thomson Microelectronics Limited

Stmicroelectronics N.v.

Sgs-Thomas Microelectronics S.a.

Jean Devin

Bruno Leconte

Alessandro Brigati

Paola Cavaleri

Sebastien Zink

David Naura

S&eacute;bastien Zink

Jean Marie Gaultier

Laurent Sourgen

Emilio Miguel Yero

Jean-Michel Mirabel

Bertrand Bertrand

Mohamad Chehadi

Marco Bildgen

Gilles Lisimaque

Philippe Calzi

Claude Costabello

Francois Maugain

A method may be for detecting potentially suspicious operation of an electronic device configured to operate in the course of activity sessions. The method may include within the device, a metering, from an initial instant of the number of activity sessions having a duration below a first threshold, and a comparison of this number with a second threshold.

Method for detecting potentially suspicious operation of an electronic device and corresponding electronic device

The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Method for programming memory cells including transconductance degradation detection

The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address of N+K bits, an extended address counter for storing an extended address received at the serial input/output of the memory, the extended address comprising N least significant bits that are applied to the integrated memory array, and K most significant bits, means for comparing the K most significant bits with the most significant address allocated to the memory, and means for preventing the execution of a command for reading or writing the integrated memory array if the K most significant address bits are different to the most significant address allocated to the memory. In one embodiment, a ready/busy pad is provided that is taken to a selected potential to prevent access to the memory.

Method and apparatus for a continuous read command in an extended memory array

A memory circuit comprising a memory area for storing data, a non-volatile memory area for storing at least one identification code, and a pin for storing the identification code in the non-volatile memory area. The memory circuit further comprising a programmable register in which a programmable state is fixed, wherein the programmable state indicates if the identification code has been stored in the non-volatile memory area, and a logic module which blocks any subsequent changes to the identification code fixed in the non-volatile memory area in response to the programmable state in the programmable register indicating that the identification code has been stored in the non-volatile area. The invention also relates to an associated method. The invention is useful particularly to avoid fraudulent reprogramming of the area containing the identification code. The invention also relates to an associated method.

Memory circuit with non-volatile identification memory and associated method

An integrated circuit having a voltage generator supplying a determined voltage, a voltage-limiting circuit arranged at the output of the voltage generator, the voltage-limiting circuit having at least one PN junction formed by a diode-arranged MOS transistor, the PN junction having a breakdown voltage defining a threshold for triggering the voltage-limiting circuit as from which the PN junction is on by avalanche effect, at least one load in series with the PN junction for limiting an avalanche current passing through the PN junction when the PN junction is on, and at least one switch in parallel with the PN junction and the load, the switch arranged in the open state when the PN junction is off and to be in the closed state when the PN junction is on.

Integrated circuit comprising a voltage generator and a circuit limiting the voltage supplied by the voltage generator

The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

Page-erasable flash memory

A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Flash memory including means of checking memory cell threshold voltages

The integrated circuit includes a detection circuit and a rectifier circuit that are series-connected, to provide a rectified voltage, and a low voltage regulation circuit that receives the rectified voltage and provides a low voltage. According to the invention, the circuit also has a voltage production circuit that receives the rectified voltage and produces a high voltage different from the low voltage. In one embodiment, the circuit also includes a memory having a memory array receiving the low voltage and the high voltage.

Voltage production circuit

Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

Set of two memories on the same monolithic integrated circuit

An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Integrated circuit comprising an output transistor with a controlled fall time

A circuit to detect and record the occurrence of a surge in the supply voltage applied to an integrated circuit includes a detection circuit for providing a control signal if a voltage surge is detected. The circuit also includes a high voltage circuit, which produces a high programming voltage from the supply voltage if a voltage surge is detected, and a memory cell. The detection circuit may include a capacitor divider bridge, a voltage source, and a comparator. The circuit is particularly advantageous for use with electrically programmable memories.

Circuit for detecting and recording a voltage surge

A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

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Le Tholonet, France

Jean Devin