Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique

Université´ D'aix-Marseille

Centre National De La Recherche Scientifique-Cnrs

Jean Coignus

Laurent Grenouillet

Sébastien Kerdiles

Elisa Vianello

Romain Wacquez

Christelle Charpin-Nicolle

Simon Jeannot

Jean-Michel Portal

Vincenzo Della Marca

William Vandendaele

Abygael Viey

Alexis Krakovinsky

Marc Bocquet

Alexandre Vernhet

Adam Dobri

Terry Francois

Jacques Cluzel

A method for co-manufacturing a FeRAM and an OxRAM includes depositing a layer of first electrode carried out identically for a zone Zand a zone Z; depositing a layer of hafnium dioxide-based active material carried out identically for Zand Z; depositing a first conductive layer carried out identically for Zand Z; making a mask at Z, leaving Zfree; removing the layer at Z, with Zbeing protected by the mask; removing the mask at Z; and depositing a second conductive layer in contact with the layer at Zand in contact with the layer at Z, the material of the layer being chosen to create oxygen vacancies in the active layer and depositing a third conductive layer carried out identically for Zand Z

Method for co-manufacturing a ferroelectric memory and an OxRAM resistive memory and device co-integrating a ferroelectric memory and an OxRAM resistive memory

A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.

Transistor characterization

A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfOpositioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.

Method for fabricating a ferroelectric memory and method for co-fabrication of a ferroelectric memory and of a resistive memory

A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.

Method for forming a non-volatile memory cell, non-volatile memory cell formed according to said method and microelectronic device comprising such memory cells

A system for characterising a NOR flash memory cell provided with a floating gate transistor, includes a voltage generator having an output connected to the gate electrode that generates as output an erase signal; and a dynamic measurement apparatus including a first channel connected to the gate electrode and a second channel connected to the drain electrode. The dynamic measurement apparatus generates on the first and second channels write signals and measures a current flowing in the drain electrode during the writing of the memory cell. Only the gate electrode of the floating gate transistor is connected to the voltage generator and to the dynamic measurement apparatus by a CMOS switch, which switches between a first position, where the output of the voltage generator is electrically coupled to the gate electrode, and a second position, where the first channel of the measurement device is electrically coupled to the gate electrode.

System for the characterisation of a flash memory cell

A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate including a channel region; a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer; a control gate positioned above the floating gate and separated from the floating gate electrode by the inter-gate dielectric structure; the method including programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer; measuring over time a change in a threshold voltage of the flash memory cell; and determining the leakage current from the change in the threshold voltage.

Method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell

A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.

Method for determining an optimal voltage pulse for programming a flash memory cell

Growing community of inventors

Grenoble, France

Jean Coignus