Compagnie Internationale Pour L'informatique Cii-honeywell Bull (societe

Jean-Claude M Cassonnet

Violette Cohen

Guy Hiot

Marie-Odile Lamarche Nee Lechevin

A controller for microinstructions grouped into microprogram segments, each of which defines a base of a microprogram segment which is to be executed, includes a bank of addressable base registers. Each register in the bank stores an indication of a base in the memory. Registers in the bank are addressed so that the addressed register derives a signal indicative of the base address. Included are an address register for the memory and an output register for microinstructions read from the memory. The address and output registers respectively have outputs and inputs coupled to an address input and a read output of the memory. An adder has inputs responsive to the base indicating signal of the addressed register and to an output of the memory output register. The adder has an output coupled to an input of the address register. The output of the memory output register is coupled to an input of the means for addressing registers in the register bank to control which register of the base register bank is addressed.

Apparatus for controlling microinstructions stored in a data processing

An arrangement for dynamically translating virtual address into absolute or physical addresses of items of data. Each virtual address includes a segment table number, a segment table entry, and a segment page number. Segment descriptors are stored in a central memory. The address of a particular segment descriptor may be calculated from the segment table number and the segment table entry. From the segment descriptor, a unique identification termed a logic page number may be calculated. The logic page number permits pseudo-associative access to a table containing a number of entries proportional to the number of physical pages of the main memory, allowing the physical address to be determined.

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Conflans Sainte Honorine, France

Jean-Claude M Cassonnet