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France Telecom

Etablissement Public De Diffusion Dit 'telediffusion De France'

Etat Francais Represent Par Le Secretariat D'etat Aux Postes Et

Etabilissement Public Dit 'telediffusion De France'

Etat Francais, Administration Des P.t.t. (centre National D'etudes Des

3g Licensing S.a.

Jean-Claude Carlach

Maryline Helard

Pierre Penard

Brahim Oueslati

Ali El Arab

Cyril Vervoux

Jean-Pierre Vigarie

Methods and devices are provided for coding and decoding coded data including source data and redundancy data. The redundancy data is obtained by applying, upon coding, an error correction code to the source data, implementing a generating matrix. The generating matrix includes, in its systematic form, an identity matrix and an invertible matrix for switching from the source data to the redundancy data. The coding or decoding is based on a Tanner graph, which combines the graph of the error corrector code and the graph of the dual code of the error correction code by superimposing these graphs.

Error corrector coding and decoding

A method for transmitting a source binary sequence, including at least one source word, in a transmission channel. The method includes the following steps, for at least one source word: error-correcting encoding the source word, outputting a code word; matrix mapping the code word, distributing bits constituting the code word within at least two mapping matrices, which are reversible and observe a criterion of uniqueness in the cancellation of a syndrome associated with the code word; and consecutively transmitting the at least two mapping matrices.

Method and device for transmission and reception in a multi-input and multi-output channel distributing a code word between several mapping matrices, and corresponding computer program

An error correction encoding device is provided that combines redundancy data with source data, said device including: at least three encoding stages and at least two permutation stages. Each encoding stage implements at least one set of three basic encoding modules, in which a first encoding stage receives said source data and a last encoding stage provides said redundancy data. Each encoding module implements a basic code and includes c inputs and c outputs, c being an integer. The permutation stages are inserted between two consecutive encoding stages and each permutation stage implements a c-cyclic permutation.

Method and device for flexible error correction encoding and corresponding computer program

The invention concerns a method and a device for error correction coding associating with a data source series a coded data block, to be transmitted to at least one receiver comprising at least two coding stages ( ) each comprising at least two basic coding modules ( ), each of said coding stages receiving a series of data to be processed, distributed between said basic coding modules, and delivering a series of processed data, derived from said basic coding modules and at least one branching stage ( ), said branching stage being inserted between two successive coding stages, a first coding stage and a second coding stage, and distributing the processed data derived from each basic coding module of said first coding stage between at least two basic coding modules of said second stage. The invention also concerns the corresponding decoding method and device, based on path likelihood.

Method and device for error correction coding and corresponding decoding method and device

A random access memory (RAM) comprises memory cells each including an RS type flip-flop having complementary data inputs and transistors for forcing the flip-flop by that one of two data wires which is at a given level (high level for example) when a selection wire is at a first given level (high level for example). The flip-flop is connected to an output wire by circuitry for maintaining the output wire at the high level as long as the selection wire is at the first level and for causing the output wire to take the level corresponding to the condition of the flip-flop when the selection wire is brought to the other level. The transistors are preferably N-MOS for higher speed.

Random access memory and linear interpolation circuit comprising

The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.

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Rennes, France

Jean-Claude Carlach