International Business Machines Corporation

International Business Corporation

Jean-Claude Abbiate

Alain R Blanc

Gerard Richter

Patrick J Jeanniot

Gottfried Ungerboeck

Michel Poret

Daniel Wind

Francois Le Maut

Bernard Brezzo

Gerard Orengo

Carl Cederbaum

Christopher G Riedle

Sylvie Gohl

Eric Lallemand

Lucien Quenel

Jean-Pierre Vaudaux

An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a processor to determine an optimum sampling position in the delay line. The processor is programmed to analyze contents of the latch by creating a sample mask from a plurality of delay line samples. The sample mask identifies transition edges of first and second data bits within the delay line. The transition edges are validated with respect to the presence, for first and second initial sampling positions for the respective data bits. New sampling positions are determined from the validated edges, and the initial sampling positions are updated with sampling positions which have been determined from the new sampling positions. In this way phase jitter induced by environmental concerns is minimized using new sampling positions along the delay line for coding the data into parallel data.

Method and apparatus for locating sampling points in a synchronous data stream

A service message system for a switching architecture including at least one Switch Fabric ( ) comprising a switch core ( ) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters ( ). Each SCAL elements particularly includes a SCAL receive element ( - ) and a SCAL Xmit element ( - ) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell. Following the Cell qualifier is the Switch Routing Header (SRH) which permits the characterization of the destination of the cell and is used for controlling the routing process. Preferably, the service message is used in a fault tolerance configuration where two different Switch Fabrics act as a standby to each other and shares a part of the traffic. Each one is configured as a default routing path for some ports adapters and a backup path for the others. In that particular configuration, the service message system of the invention uses the first field of the Cell qualifier to transport a Direct filtering command causing the Switch fabric to route the cell when the SRH is representative of its default output port destination. Conversely, the first field may transport a Reverse filtering command in the first field that causes the Switch fabric to reverse the default routing process. The first field is also used for characterizing a service message cell which the second field indicates the accurate type. Particularly, two types are used for the production of the filling cells when no data cell is to be transmitted at a particular location of the switching architecture.

Service message system for a switching architecture

A method and circuit for comparing the frequencies of two clocks (clock and clock ), without taking into account their phase, is disclosed. Each clock is associated to a circular counter ( - and - ) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock and clock ) are equal, both counters ( - and - ) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters ( - and - ) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters ( - and - ) are 2-bit circular counters.

Phase independent frequency comparator

The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.

System and method for a self-delineating serial link for very high-speed data communication interfaces

A process for transporting a data cell throughout a switch fabric having a centralized switching structure and a set of distributed, generally remotely located, Switch Core Access Layers (SCAL) permitting the attachment of the protocol adapters. Remotely with respect to the centralized switching structure, the data cell which is received from a telecommunications link is divided into k logical units (LUs) and additional bytes are introduced for permitting the reservation of a bitmap field that will be used for routing through the switch core. Every LU is coded in accordance with the 8B/10B coding process. Within the centralized switching structure, the k coded LUs are deserialized and the cell clock is obtained for each cell in order to reconstitute the data cell. In addition the routing byte reservations are filled with appropriate values (bit map) for the routing process within the switch by means of an access to an entry routing table. When the cell outputs the switching structure, a second access to a routing table permits the replacement of the previous bit map by new values in order to enhance multicast capabilities. The data cell is divided again in a set of k serialized logical units (LUs) in order to prepare a serialization through k links. The LUs are coded as previously to permit the merging of the LUs when different sets of switches operated in parallel are connected in a port expansion mode. Remotely with respect to the switch core, the coded LUs are deserialized and the data cell is reconstituted by means of the deserialization and extraction of the data cell clock transported by the 8B/10B coding process. The newly inserted values of the bit map are then used for enhancing multicasting capabilities.

Process for transporting a cell through a switching structure base on a single stage switch

A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter which corresponds to a determined decimation factor, and the PCM samples being processed by a Digital Signal Processor (DSP). The decimation filter includes a device for storing a digital value representative of the DC component introduced during the sigma-delta coding process, with the digital value being computing by the DSP processor during an initialization phase. The decimation filter further includes a device operating after the latter initialization phase for subtracting the stored digital value from each of the PCM samples so that the resulting sequence of PCM samples appears free of any DC component introduced during the sigma-delta coding. This accurate DC component suppression is achieved without necessitating the use of additional digital signal processor resources from the processor. Preferably, the decimation filter comprises a device for detecting a saturation occurring in the computing of the PCM sample, and responsive to the saturation detection, for transmitting a predetermined PCM sample to the DSP processor.

Decimation filter for a sigma-delta converter and A/D converter using

A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.

Decimation filter for a sigma-delta converter and data circuit

Data Circuit Terminating Equipment (DCE) allows the connection of a Data Terminal Equipment (DTE) to a telecommunication line. The DCE includes timing elements for providing the DTE with any desired transmitter signal element timing and any desired receiver signal element timing. The timing elements include processing elements for computing a sequence of digital values A(n) and for deriving therefrom a corresponding sequence of interrupt signals T(n). The receiver signal element timing, the transmitter signal element timing, the transmit sampling clock pulsing the D/A converter and the receive sampling clock pulsing the A/D converter are all controlled by different sequences of digital values computed by the processing elements. By generating appropriate sequences of digital values, the processing elements can provide any desired relationship between the different clocks to satisfy a transmit signal element timing slaved to the receiver signal element timing in synchronous mode, or on an external clock in tailing mode. The timing elements can also provide a transmit sampling clock slaved to the receive sampling clock in order to perform powerful digital echo cancellation techniques. Moreover, the processing elements can control the persistence of a received bit, which if a STOP bit, can allow the compensation of the DTE and the line data throughput difference.

Data circuit terminating equipment (DCE) including timing arrangements

A system implemented in a Data Circuit Terminating Equipment (DCE), interfacing between a user's data processing equipment and a digital network, comprises a detector for generating an Analog Carrier Detect (ACD) DCE internal signal as well as an Analog Squared Data (ASD) DCE internal signal, and an ASD WIDTH ERROR DCE internal signal from the flow of data transmitted by the network and received on the DCE receive line. The system also comprises new circuitry for generating a Lack of Receiver Timing (LRT) DCE internal signal, a Block Error ASD DCE internal signal, and a Block Error Bipolar (BEBIP) DCE internal signal. Finally, the system includes a logical decision process which leads the DCE to automatically adjust its functional speed to the rate of data transmitted by the network and received on DCE receive line. The process includes setting the DCE to the highest possible functional speed, and for that particular speed, checking all four of the ACD, LRT, BEASD and BEBIP DCE internal signals; and if one of the checkings is not satisfactory, setting the DCE to the next possible lower speed, or if all checkings are satisfactory, stopping the process as the DCE is ready to work.

Method and apparatus for automatic functional speed setting of a data

A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##

Decimation filter in a sigma-delta analog-to-digtal converter

An adaptive equalization system for allowing the equalization of a base-band line of a DCE within a predetermined range, includes an adaptive equalizer for continuously adapting its coefficients in accordance with a predetermined adaptive algorithm. The equalizer includes storage for a plurality of sets of initial coefficients for the equalization process corresponding to a plurality of telecommunication line characteristics and circuits for estimating the energy of the received signal. From the estimation of the energy of the signal on the line, there is derived one set among the plurality of sets of initial coefficients which are then used for setting the equalization before initiating the convergence process. An efficient and very simple equalization process is therefore provided which is ensured to converge whatever the characteristics of the line within the considered range.

Adaptive equalization system and method for equalizing a signal in a DCE

Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal from at least one feedback loop. The sigma-delta converter further includes circuits (221, 222) located in said feedback loop for performing a return-to-zero of the sigma-delta code generated by said threshold device at every period of the sigma delta clock, whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall time of the threshold device. This results in an increase of the signal-to-noise ratio and linearity of the converter, allowing the manufacture of a sigma-delta convertor with discrete components without requiring the development of an integrated circuit using switched capacitor technology.

Sigma delta converter insensitive to asymmetrical switching times

A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive previous transitions. A phase locked oscillator which is driven by said SPL pulse generates the extracted clock signal which is in phase with the SPL pulse and coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs. The result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. The preferred embodiment of the invention also involves an up/down counter K which generates a second counter K(i) that is expected to be representative of half the value of the first counter N(i). Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor.

Predictive clock recovery circuit

An interface device for synchronizing an internally clocked modem and data terminal equipment (DTE) provided with their own clock circuits, each of said own terminal clock circuit providing an external clock signal (RC Ext). The interface includes a PLO generating a recovered clock signal (XCO). At a moment defined by a request to send signal the phases of XCO and RC Ext are compared with each other and a switched clock signal SWC oscillating at a fast rate for a time interval corresponding to the phase delay between RC Ext and XCO and subsequently oscillating at a slow rate, is generated. The signal SWC is used for shifting RC Ext and terminal provided data RD Ext into shift registers respectively. The shifted RC Ext is used for controlling the adjustment of the interface PLO.

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La Gaude, France

Jean-Claude Abbiate