Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Stmicroelectronics Gmbh

Jean-Christophe Giraudin

Sébastien Cremer

Philippe Delpech

Philippe Coronel

Michel Marty

Guillaume Bouche

Vincent Fiori

Thierry Jagueneau

Christine Rossato

Emmanuelle Serret

A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.

Manufacture of 3 dimensional MIM capacitors in the last metal level of an integrated circuit

A monolithic assembly of electronic components including a semiconductor substrate, at a first level above the substrate, at least one bulk acoustic wave resonator, at a second level above the resonator, a single-crystal semiconductor layer in which are formed semiconductor components, and recesses under the semiconductor layer portions arranged above the resonators.

Component containing a baw filter

An integrated circuit includes at least one capacitor that is formed on a layer provided with at least one first trench. The capacitor, which is provided with a dielectric layer that separates two electrodes, conforms to the shape of the first trench, but leaves a part of the first trench unfilled. A material capable of absorbing stresses associated with the displacements of the walls of the trench is placed in the trench to fill the part of the first trench. A second trench is formed at least partly surrounding the first trench. This second trench is also at least partly filled with a material capable of absorbing stresses associated with the displacements of the walls of the second trench. A void may be included in the stress absorbing material which fills either of the first or second trenches.

Integrated circuit comprising at least one capacitor and process for forming the capacitor

A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (); Deposit of a first insulator layer () on the first metallic layer (); Deposit of a second metallic layer () on the first insulator layer (); Formation of an upper electrode () in the second layer metallic (); Deposit of a second insulator layer () covering the upper electrode (); Etching of the second insulator layer to form a spacer () on this first insulator layer surrounding the upper electrode (); then Formation of a lower electrode () and a dielectric () by removal of parts from the first metallic layer and insulator not covered by the upper electrode () or the spacer (); and Formation of an interconnection line (). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit

An integrated circuit is produced to include interconnection levels each incorporating a metallization level covered with an insulating material. The integrated circuit includes at least one capacitor possessing at least one part lying within a single interconnection level. The capacitor is produced before the interconnection level is produced. The covering of part of the capacitor with an insulating protective layer occurs before the metallization level of the interconnection level is produced.

Process for producing an integrated circuit comprising a capacitor

A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

Method for fabricating an integrated circuit comprising a three-dimensional capacitor

A process for producing a capacitor integrated into an electronic circuit comprises the formation of a trench in a substrate through a conductive portion similar to an MOS transistor gate. Alternating conductive, insulating and conductive layers are deposited inside the trench T in order to form a lower electrode, a dielectric and an upper electrode of the capacitor, respectively. The conductive portion is used to electrically connect the lower electrode to other electronic components of the circuit without an additional cost with respect to the connection of the circuit transistors.

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Bernin, France

Jean-Christophe Giraudin