Sensio Technologies Inc.

3dn, LLC

Ecole De Technologie Superieure

Socovar Sec

Jean Belzile

Claude Thibeault

Nicholas Routhier

Daniel Malouin

Pierre-Paul Carpentier

Martin Dallaire

François Gagnon

Patrick Rioux

Naïm Batani

Naim Batani

A method for decoding a compressed image stream, the image stream having a plurality of frames, each frame consisting of a merged image including pixels from a left image and pixels from a right image. The method involves the steps of receiving each merged image; changing a clock domain from the original input signal to an internal domain; for each merged image, placing at least two adjacent pixels into an input buffer and interpolating an intermediate pixel, for forming a reconstructed left frame and a reconstructed right frame according to provenance of the adjacent pixels; and reconstructing a stereoscopic image stream from the left and right image frames. The invention also teaches a system for decoding a compressed image stream.

Process and system for encoding and playback of stereoscopic video sequences

The present invention provides for a method that could be advantageously implemented in a satellite local area network (LAN) in which an average number of sites share a TDMA link. The invention provides for both a dedicated bandwidth to all the sites and a shared bandwidth that is dynamically assigned to the sites, therefore allowing for both synchronous traffic and for on request burst mode traffic. The method includes a reservation method of this shared bandwidth which is specially optimized for a satellite link. The method provides also for a network that automatically managed its communication bandwidth resources and the synchronization of the sites, without the need of an external controller. The present invention also provides for a satellite modem to transmit data from a site, to receive data from the sites and to manage the bandwidth resources of the TDMA satellite in accordance with the above method.

Satellite modem with a dynamic bandwidth

A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.

Method and apparatus for testing a device in an electronic component

A digital parallelized Infinite Impulse Response (IIR) integrator filter comprising a first channel having a first input and second channel having a second input, a first adder to add the two channel inputs, an integrator to integrate the added channel inputs to provide a first channel output is described herein. The second input channel is adjacent in time to the first channel input. The second channel further comprises a second adder which adds the first output with the second channel input in order to produce a second output, adjacent in time with the first output. This configuration can be generalized to n inputs and m outputs.

Parallelized infinite impulse response (IIR) and integrator filters

A synchronous clocking method and apparatus is disclosed for clocking a plurality of processing units. Each of the plurality of processing units is connected to at least another one using an interblock synchronization signal. Upon receipt of the interblock synchronization signal, data is provided between at least two processing units.

Growing community of inventors

Lachine, Canada

Jean Belzile