Stmicroelectronics S.a.

Sgs-Thomson Microelectronics S.a.

Jean Barret

Daniel Quessada

Antoine Pavlin

Alain Bailly

Pietro Fichera

The invention concerns a control circuit () of a switch () chopping a voltage supply of a primary winding of a power converter transformer, comprising means () for detecting the current in the switch in closed state after a predetermined time following each closure of said switch, and a comparator () of said current relative to a threshold (Ilim), the result of said comparator being taken into account for a predetermined time interval close to the beginning of a closing cycle of said chopping switch.

Limiting the continuous mode of a power converter

The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N-type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.

Component of protection of an integrated MOS power transistor against

The present invention relates to a protection device for a component including a vertical MOS power transistor and logic components. The protection device includes a first zener diode, a first terminal of which corresponds to the substrate and a second terminal of which corresponds to a region of the second type of conductivity formed in the substrate. It also includes a second zener diode of the same type of conductivity as the first zener diode but of higher avalanche voltage, the second terminals of both zener diodes being connected to a circuit for starting the power transistor via a logic circuit which only becomes conductive when one of its inputs is high and distinct from the other input.

Protection against overvoltages of an integrated MOS power transistor

A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.

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Eguilles, France

Jean Barret