Stmicroelectronics S.a.

Centre National De La Recherche Scientifique

Stmicroelectronics (Grenoble 2) Sas

Centre National Detudes Spatiales

Jean-Baptiste Begueret

Didier Belot

Eric Kerherve

Yann Deval

Franck Badets

Dominique Dallet

André Mariano

Thierry Taris

Francois Rivet

Michel Pignol

Nicolas Regimbal

Hervé Lapuyade

Cédric Majek

Pierre Melchior

Vincent Lagareste

Olivier Mazouffre

Claude Neveu

Pierre-Olivier Lucas De Peslouan

Bernardo Leite

Continuous time analog/digital converter, comprising a sigma delta modulator (MSD) configured to receive an analog input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD).

Continuous time analogue/digital converter

A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period.

Fractional frequency divider

Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider.

Device and method for generating a signal of parametrizable frequency

Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD).

A device for extracting a clock signal from a baseband serial signal, includes an injection-locked oscillator (), a phase-locked loop () including a digital phase detector (). The oscillator () includes a digital input for controlling the value of its natural frequency, and the phase-locked loop () includes a counting circuit () aggregating the relative values of the digital signal supplied by the digital phase detector () and supplying a control signal in digital form for the oscillator ().

Clock extraction device with digital phase lock, requiring no external control

A device processes a received radio signal. Circuitry formulates voltage samples of the radio signal. Analog processing of those samples is performed. Then, digital processing is performed on the output of the analog processing. The circuitry for formulating voltage samples is configured to ensure a processing of the samples prior to the digital processing.

Method and device for the analog processing of a radio signal for a radio frequency receiver

A method is for reducing a DC component of an input signal transposed into baseband and being generated by a first frequency transposition stage starting from an initial signal and from a transposition signal. The method includes amplifying the transposed input signal in a first amplifier. The first amplifier receives at a DC offset compensation input, a compensation signal extracted from an output signal of a second amplifier subjected to a compensation of a offset DC voltage of the second amplifier. The method also included alternating between receiving at an input of the second amplifier, a first auxiliary signal from an auto-transposition of a transposition signal in a second frequency transposition stage and a second auxiliary signal from a transposition of the initial signal in the second frequency transposition stage with the transposition signal.

Method and device for the reduction of the DC component of a signal transposed into baseband, in particular in a receiver of the direct conversion type

A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.

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Merignac, France

Jean-Baptiste Begueret