Samsung Electronics Co., Ltd.

Je-Min Yu

Ho-Young Song

Sang-Joon Hwang

Sung-Min Seo

In-Chul Jeong

Byung-Chul Kim

Jun-hyung Kim

Chi-wook Kim

Jong-Min Oh

Gil-Su Kim

Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Semiconductor memory device having OTP cell array

A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Semiconductor memory device including sensing verification unit

A semiconductor memory device includes a bitline sensing amp detecting and amplifying data of a pair of bitlines from a memory cell, a column selecting unit transmitting the data of the pair of bitlines to a pair of local datalines in response to a column selecting signal, a dataline precharging unit precharging the pair of local datalines to a precharging voltage level in response to a precharging signal, and a dataline sensing amp detecting and amplifying data transmitted to the pair of local datalines. The dataline sensing amp includes a charge sync unit discharging the pair of local datalines at the precharging voltage level in response to a first dataline sensing enabling signal and data of the pair of local datalines, and a data sensing unit transmitting data of the pair of local datalines to a pair of global datalines in response to a second dataline sensing enabling signal.

Semiconductor memory device

A memory core capable of decreasing the area of core conjunction region is disclosed. The memory core includes a first sub word-line driving circuit and a first sub word-line control signal generating circuit. The first sub word-line driving circuit is disposed in a first region, and generates a first word-line driving signal to provide the first word-line driving signal to an array unit. The first sub word-line control signal generating circuit is disposed in the first region, and generates the first sub word-line control signal based on a sub word-line driving signal. Therefore, the memory core has a small size and, consequently so can the semiconductor device.

Memory core and semiconductor memory device having the same

A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.

Growing community of inventors

Seoul, South Korea

Je-Min Yu