Finisar Corporation

Jayne Catherine Hahin

Gerald L Dybsetter

Luke M Ekkizogloy

Lucy G Hosking

Stephen T Nelson

Daniel K Case

Lewis B Aronson

Arthur Michael Lawson

Willem A Mostert

William H Ellis

Luke M Ekkisogloy

Gerald L Dybesetter

Jerry Dybsetter

A mechanism for an optical transceiver to log information about its operational parameters to an off transceiver host computing system (hereinafter referred to simply as a 'host'). The optical transceiver may be communicatively coupled to the host. The optical transceiver is configured to identify operational information regarding itself. The operational information may include statistical data about operation, or may include measured parameters. The optical transceiver may log the information to the memory of the host in an off transceiver logging operation.

Optical transceiver with off-transceiver logging mechanism

Two or more optical transceivers coupled to each other by an optical link to optimize communication over the optical link. A first transceiver generates electrical data that represents an operational parameter for optimization. The transceiver then converts the electrical data into an optical signal and transmits the optical signal over the optical link to a second transceiver. The second transceiver recovers the electrical data from the optical signal and uses the recovered electrical data to change characteristics of the optical signal transmitted by the second transceiver.

Inter-transceiver module communication for optimization of link between transceivers

A two-wire interface in which upon determining that an operation is to be performed on a slave component, the master component monitors the data wire for a predetermined number of consecutive bits having a particular binary value. Upon detection such a sequence, the master component asserts a frame of a two-wire interface on the data wire. This detected predetermined number of consecutive bits will be considered to be the preamble. During at least some of the preamble phase, the master component is not asserting anything on the data wire. Instead, the data wire is pulled high (or low) by a weak pull-up (or pull-down) resistor. Furthermore, the frame is designed so that there are bits having a guaranteed binary value that is opposite what would be expected in the preamble, to thereby facilitate synchronization.

Two-wire interface in which a master component monitors the data line during the preamble generation phase for synchronization with one or more slave components

An optical transceiver configured to perform filtering of digital diagnostics prior to the filtered results being made accessible to a host computing system (hereinafter referred to simply as a 'host') that is communicatively coupled to the optical transceiver. The optical transceiver includes sensor(s) that measures analog operational parameter signals such as temperature and supply voltage. The analog signals are each converted to a plurality of digital samples by analog to digital converter(s). A processor executes microcode that causes the optical transceiver to perform filtering on the various samples. The optical transceiver may then make the filtered result accessible to the host.

Filtering digital diagnostics information in an optical transceiver prior to reporting to host

An operational optical transceiver configured to update operational firmware using an optical link of the transceiver. The optical transceiver includes at least one processor and a system memory capable of receiving firmware. The optical transceiver receives an optical signal over the optical link containing the update firmware. The optical transceiver then recovers the firmware from the optical signal. Finally, the optical transceiver provides to the system memory the recovered firmware, which when executed by the at least one processor alters the operation of the transceiver.

Inter-transceiver module communication for firmware upgrade

An operational optical transceiver configured to self-validate a boot image loaded from the persistent memory early in the boot process. The optical transceiver includes a persistent memory, a controller, and a system memory. The controller initializes the boot process and begins to load information from the persistent memory to the system memory. Next, the controller detects early in the boot process boot image verification data in the information being sent to the system memory. The controller then determines if the boot image verification data has an expected value. If the verification data includes the expected value, the controller continues the boot process. If the verification data does not include the expected value, the controller will retry the boot process a predetermined number of times and will enter a default operational state if the expected value is not detected while retrying the boot process the predetermined number of times.

Early self-validation of persistent memory during boot in an optical transceiver

An optical transceiver (or optical transmitter or optical receiver) that includes a memory and a processor, which receives and executes custom microcode from a host computing system (hereinafter referred to simply as a 'host'). A user identifies desired optical transceiver operational features, each of which may be implemented using specific microcode. The memory receives custom microcode that aggregates all the specific microcode of the identified operational features from the host. The processor may later execute the custom microcode and cause the transceiver to perform the operational features.

Configuration of optical transceivers to perform custom features

A mechanism that enables an optical transceiver to grant access to its memory on a per-segment basis. The optical transceiver includes a processor, system memory and a memory access table. The memory access table is comprised of access entries, each of which defines the access condition for a corresponding segment of memory. The processor reads the access entries for a particular segment of the memory. The processor or other optical transceiver component then determines whether or not to grant access to the memory segment based on the access entry read by the processor. Different levels of access control may be accommodated.

Multi-level memory access in an optical transceiver

A mechanism that enables an optical transceiver to configure memory on a per-segment basis. The optical transceiver includes a processing entity, system memory and a memory configuration table. The memory configuration table is comprised of configuration entries, each of which defines the configuration setting for a corresponding segment of memory. The processing entity reads the configuration entries for a particular segment of the memory. The processing entity then determines the set of one or more configuration settings for the memory segment based on the configuration entry read. This process may be repeated for multiple segments of memory.

Byte-configurable memory in an optical transceiver

An environment that facilitates the purchasing and updating of specific operational features in an optical transceiver (or optical transmitter or optical receiver). The environment includes a host computing system (hereinafter referred to as the 'host'), a network, a remote computing site, and an optical transceiver having a system memory and at least one processor. The host determines that microcode that governs the behavior of an optical transceiver is desired to be purchased. A request to purchase the microcode is sent over the network from the host to the remote computing site. The remote computing site responds to this request by providing the host information by which the purchased microcode may be accessed. The host may then access the microcode. Finally, the host provides the microcode to the optical transceiver memory where it may later be executed by the processor.

Transaction for transceiver firmware download

An environment that facilitates the purchasing and updating of specific operational features in an optical transceiver (or optical transmitter or optical receiver). The environment includes a host computing system (hereinafter referred to as the 'host'), a network, a remote computing site, and an optical transceiver having a system memory and at least one processor. The host determines what specific operational feature is desired. A request to purchase the specific operational feature is sent over the network from the host to the remote computing site. The remote computing site responds to this request by providing the host information by which microcode corresponding to the purchased specific feature may be accessed. The host may then access the feature specific microcode. Finally, the host provides the feature specific microcode to the optical transceiver memory where it may later be executed by the processor.

Configurable optical transceiver feature specific cost transaction

An operational optical transceiver (or transmitter or receiver) configured to contain a module command interface. The optical transceiver includes at least one processor, a memory location dedicated for high level commands, and a library of microcode that control specific optical transceiver operations. A high level command is written to the memory location dedicated for high level commands. The processor determines that the high level command has been written to the memory location, identifies what the command is, and executes microcode from the microcode library that corresponds to the high level command. The executed microcode causes the optical transceiver to perform the operation directed by the high level command.

Module command interface for an optical transceiver

An operational optical transceiver configured to initiate operation in loop back mode. The optical transceiver includes transmit and receive signal paths, a memory capable of having microcode written to it, and a configurable switch array that is used to connect and disconnect the two signal paths as appropriate for a desired loop back mode. The microcode is structured to cause the optical transceiver to control the configurable switch array. This allows for analysis and diagnostics of the signal data.

Transceiver based loop back initiation

A method for dynamically updating an optical transceiver (or optical transmitter or optical receiver) that has at least one processor, a persistent memory, and a microcode loader mechanism. The persistent memory includes microcode comprising instructions that, when executed by the at least one processor, control at least one component of the optical transceiver, transmitter, or receiver. In order to implement the invention, data is written to the persistent memory of the optical transceiver to indicate that an updating of microcode currently stored on the persistent memory is to occur. The optical transceiver processes received microcode, which contains instructions that are structured such that when executed by the at least one processor of the optical transceiver, the execution of the instructions affects the operation of the optical transceiver. Then, the processed representation of the received microcode is written to the persistent memory. The optical transceiver then determines that all of the microcode that is to be written to the persistent memory during the update has been written to the persistent memory. Finally, the persistent memory is altered to reflect that the update is complete.

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Cupertino, CA, United States of America

Jayne Catherine Hahin