Taiwan Semiconductor Manufacturing Comp. Ltd.

Jaymeen Bharatkumar Aseem

Ching-Wei Wu

Pankaj Aggarwal

A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates.

Circuit and method of writing to a bit cell

A circuit includes a bit line, a pass gate coupled between the bit line and a power node having a first power voltage level, and a driver coupled between the bit line and a reference node having a reference voltage level. The pass gate couples the bit line to the power node when the first signal has the reference voltage level and decouples the bit line from the power node when the first signal has the first power voltage level. The driver receives a second signal based on a control signal, couples the bit line to the reference node when the second signal has a second power voltage level below the first power voltage level, and decouples the bit line from the reference node when the second signal has the reference voltage level. An input circuit generates the first signal independent of the control signal.

A circuit includes a bit line, a power node having a first power voltage level, a reference node having a reference voltage level, a pass gate coupled between the bit line and the power node, and a driver coupled between the bit line and the reference node. The pass gate couples the bit line to the power node responsive to a first signal, and the driver couples the bit line to the reference node responsive to a second signal. The first signal is based on the first power voltage level, and the second signal is based on a second power voltage level between the reference voltage level and the first power voltage level.

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Hsinchu, Taiwan

Jaymeen Bharatkumar Aseem