Netlist, Inc.

Viking Components

Jayesh R Bhakta

Jeffrey C Solomon

Hyun K Lee

Chi-She Chen

Scott H Milton

Chi She Chen

Robert S Pauley, Jr

William M Gervasi

Mario Jesus Martinez

Jose Delvalle

Soonju Choi

Enchao Yu

Richard E Flaig

Jefferey C Solomon

Hao Le

Jeffery C Solomon

Soon J Choi

Mike Hossein Amidi

Kavous Vakilian

Son H Nguyen

A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.

Multi-mode memory subsystem including control and data modules for buffering and testing

In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

Memory with on-module power management

A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

Memory module with data buffering

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller. The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.

Memory module with local synchronization and method of operation

A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n<N) data path and logic configurable to, in response to the second module control signals, enable the n-bit-wide data path to receive and regenerate signals carrying a respective n-bit-wide section of the N-bit-wide data communicated from/to a respective n-bit-wide section of the module data lines. The logic is further configurable to disable the n-bit-wide data path when the memory module is not being accessed for data.

Memory module with distributed data buffers

A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.

Multi mode memory module with data handlers

A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

Memory module with timing-controlled data buffering

A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

Memory module having volatile and non-volatile memory subsystems and method of operation

A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

Hybrid memory module and system and method of operating the same

Flash-dram hybrid memory module

A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.

Flash-DRAM hybrid memory module

A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.

Memory module with controlled byte-wise buffers

A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.

Growing community of inventors

Cerritos, CA, United States of America

Jayesh R Bhakta