Intel Corporation

International Business Machines Corporation

Jayesh M Joshi

James P Kardach

Patrick M Bland

Sung Soo Cho

Neil W Songer

Robert T Jackson

Nicholas B Peterson

Thomas R Lane

Richard Gerard Hofmann

Nader Amini

Sham M Datta

Bechara F Boury

Grant L Clarke, Jr

A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

Serial interrupt bus protocol

A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per interrupt request input. The present invention also includes interrupt selection logic which outputs a particular interrupt in response to an interrupt request input and data stored in the programmable register. The interrupt then invokes the associated interrupt service routine to handle the interrupt request. The present invention is used to choose the interrupt service routine to handle a particular interrupt request from any source within the computer system in any computer system operating mode.

Method and apparatus for selectively invoking a particular interrupt

A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers samples information from a system bus. Such information is obtained by a register accessing the plurality of system management shadow registers through a common shadow port.

System management shadow port

A device and method for power management of direct memory access ('DMA') slaves through DMA traps. The device comprises a plurality of registers coupled with conventional logic in order to generate a control signal for disabling direct memory access transfer requests for a powered-off DMA slave until the slave is re-powered. The method for managing power comprises steps of unmasking bits in a register containing information regarding which DMA slaves have been powered-off. Next, the DMA Controller consults a power management macro ('PMM') to determine whether a DMA transfer request involves a powered-off DMA slave. If not, the DMA transfer continues. However, if the DMA transfer does involve a powered-off DMA slave, then a main software application in operation is temporarily halted and the PMM generates a SMI signal and outputs the SMI signal to the central processing unit ('CPU') while keeping the disable control signal asserted, which effectively disables the DMA channel. The SMI signal invokes a software service routine which re-powers the powered-off DMA slave so that the main software application can continue.

Power management of DMA slaves with DMA traps

The present invention relates to an apparatus and method for controlling a CPU clock in response to certain events with a system in order to conserve power usage. These events can be programmably enabled or disabled. The apparatus comprises a circuit for detecting enabled Stop Clock events requiring the CPU clock to temporarily cease operation. In combination therewith, the present invention includes a circuit for detecting enabled Stop Break events which are used to re-start the CPU clock. The present invention further comprises a Speedup circuitry to increase the CPU clock speed for enabled speedup events which are dependent on CPU clock speed.

CPU clock control unit

A method and mechanism for suspending and resuming a keyboard controller. The present invention includes a method and mechanism for saving the state of an input device, such as a keyboard and/or mouse, such that the power to those devices may be removed. The keyboard controller of the present invention is capable of performing a password security function. The present invention allows the keyboard controller to be suspended and resumed without jeopardizing the password security function.

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Santa Clara, CA, United States of America

Jayesh M Joshi