Samsung Electronics Co., Ltd.

Jayeon Lee

Yeongkwon Ko

Jaekyung Yoo

Teak Hoon Lee

Jae-Eun Lee

Jin-woo Park

Jin-Woo Park

Teakhoon Lee

Jaeeun Lee

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Semiconductor package and method of fabricating the same

A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

Semiconductor package including part of underfill on portion of a molding material surrounding sides of logic chip and memory stack on interposer and method for manufacturing the same

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Seongnam-si, South Korea

Jayeon Lee