International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Jaydip Bhaumik

Raymond Alan Richetta

Rick Allen Philpott

Chad Edward Mitchell

Klaas Berend Klaassen

Robert Andrew Kertis

Jacobus Cornelis Leonardus Van Peppen

A method and apparatus are provided for optimizing calibration of a tunable filter over a wide range of frequencies in a data channel of a direct access storage device (DASD). Calibration codes are received for low corner frequency, banding, and high corner frequency. A programmable diode is provided with a DC portion and a tunable digital-to-analog converter (DAC). A calibration control current is generated for calibrating the tunable filter utilizing the programmable diode and the calibration codes. The programmable diode is used to vary the calibration control current to calibrate the tunable filter to a correct low corner frequency and high corner frequency. The programmable diode can be programmed over a large range.

Method and apparatus for optimizing corner frequency calibration of a tunable filter using a programmable diode

A system and method provides for calibrating a corner frequency of a tunable filter coupled to a read channel of a data storage system to a desired frequency. A signal having a frequency equal to the target corner frequency is generated. A gain of the signal is adjusted to a gain threshold. The gain of the signal is then increased from the gain threshold by a pre-established amount, such as by 3 dB. The corner frequency of the signal is shifted until the gain of the signal is substantially equal to the gain threshold, at which point the corner frequency of the tunable filter is calibrated to the desired frequency. The signal generated is a peak-detectable signal. The corner frequency of a tunable filter may be a low or high corner frequency appropriate for filtering a data signal or a servo signal. The corner frequency calibration circuitry may be implemented in-situ the read channel circuitry of a data storage system.

System and method for calibrating a corner frequency of a tunable filter employed in a read channel of a data storage system

A system and method are provided for calibrating a corner frequency of a tunable filter using an ADC code difference method. A method for calibrating a corner frequency of a tunable filter in a direct access storage device includes generating a signal having a frequency within a pass band of the tunable filter to be passed to the tunable filter. The gain of the signal is adjusted to a first threshold level. The corner frequency of the signal is shifted to a second threshold level, whereby the corner frequency of the tunable filter is calibrated at a desired frequency. A system for calibrating a corner frequency of a tunable filter in a direct access storage device includes calibrate control logic coupled to a tunable filter. A signal source generating a signal having a frequency within a pass band of the tunable filter to be passed to the tunable filter is coupled to the tunable filter by a variable gain amplifier. An analog-to-digital converter (ADC) is coupled to the tunable filter. The ADC produces a digitized signal in response to receiving the signal from the filter. The calibrate control logic adjusts a gain of the digitized signal to a first threshold level. The calibrate control logic shifts the corner frequency of the digitized signal to a second threshold level, whereby the corner frequency of the tunable filter is calibrated at a desired frequency. The first threshold level is set to a first ADC code and the second threshold level is set to a second ADC code. The second threshold level, second ADC code is set to the equivalent code of any given attenuation setting, for example, about 3 dB less than the first threshold level, first ADC code.

System and method for calibrating a corner frequency of a tunable filter using ADC code difference method

A circuit arrangement for correcting magneto-resistive head asymmetry includes a shift circuit which receives a read signal from a magneto-resistive head, and a polarity signal indicative of the polarity of any asymmetry of the read signal. Depending on the polarity of the asymmetry, the shift circuit either adds or subtracts a shift voltage to the read signal to produce a shifted read signal. The shift circuit outputs the read signal, the shifted read signal, and the shift voltage. First, second and third gain circuits are provided, which receive the read signal, the shifted read signal, and the shift voltage, respectively, and which each receive a respective control signal. The first, second and third gain circuits provide respective outputs amplified proportionally based on the respective control signals. Control circuitry provides the polarity signal to the shift circuit and the respective control signals to the first, second and third gain circuits, based on an amount of correction required. A common-mode-feedback circuit adjusts for changes in the common-mode caused by the waveform shaping.

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Rochester, MN, United States of America

Jaydip Bhaumik